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A 90nm CMOS Gated-Ring-Oscillator-Based 2-Dimension Vernier Time-to-Digital Converter

Lu, Ping LU ; Liscidini, Antonio and Andreani, Pietro LU (2012) Norchip conference, 2012
Abstract
Two branches of gated ring oscillators (GRO)

act as the delay lines in 2-dimension Vernier

time-to-digital converter (TDC). The proposed

architecture reduces dramatically the inherent latency of

vernier structure. The already small quantization noise of

the standard Vernier TDC is further first-order shaped by

the GRO operation. The TDC has been simulated in 90nm

CMOS technology. Operating from 50MHz reference

frequency, it achieves a resolution better than 2ps

assuming a signal bandwidth of 1.56MHz (OSR=16), for a

minimum current consumption of 1.8mA from 1.2V.
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Contribution to conference
publication status
in press
subject
keywords
Digitall PLL, TDC, GRO, 2-dimention
pages
4 pages
conference name
Norchip conference, 2012
language
English
LU publication?
yes
id
1c33fdf2-a482-49f5-8e14-262b77c63ac1 (old id 3130166)
alternative location
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6403120&contentType=Conference+Publications&searchField%3DSearch_All%26queryText%3DA+90nm+CMOS+gated-ring-oscillator-based+2-dimension+Vernier+time-to-digital+converter
date added to LUP
2012-10-17 12:11:59
date last changed
2016-07-13 13:42:40
@misc{1c33fdf2-a482-49f5-8e14-262b77c63ac1,
  abstract     = {Two branches of gated ring oscillators (GRO)<br/><br>
act as the delay lines in 2-dimension Vernier<br/><br>
time-to-digital converter (TDC). The proposed<br/><br>
architecture reduces dramatically the inherent latency of<br/><br>
vernier structure. The already small quantization noise of<br/><br>
the standard Vernier TDC is further first-order shaped by<br/><br>
the GRO operation. The TDC has been simulated in 90nm<br/><br>
CMOS technology. Operating from 50MHz reference<br/><br>
frequency, it achieves a resolution better than 2ps<br/><br>
assuming a signal bandwidth of 1.56MHz (OSR=16), for a<br/><br>
minimum current consumption of 1.8mA from 1.2V.},
  author       = {Lu, Ping and Liscidini, Antonio and Andreani, Pietro},
  keyword      = {Digitall PLL,TDC,GRO,2-dimention},
  language     = {eng},
  pages        = {4},
  title        = {A 90nm CMOS Gated-Ring-Oscillator-Based 2-Dimension Vernier Time-to-Digital Converter},
  year         = {2012},
}