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A Continuous Time Delta-Sigma Modulator with Reduced Clock Jitter Sensitivity through DSCR Feedback

Radjen, Dejan LU ; Andersson, Martin LU ; Sundström, Lars and Andreani, Pietro LU (2012) In Analog Integrated Circuits and Signal Processing
Abstract
The performance of continuous time deltasigma

modulators is limited by their large sensitivity to

feedback pulse-width variations caused by clock jitter in

their feedback DACs. To mitigate that effect, a dual switched-

capacitor-resistor feedback DAC technique is proposed.

The architecture has the additional benefit of

reducing the typically high switched-capacitor-resistor

DAC output peak currents, resulting in reduced slew-rate

requirements for the loop-filter integrators. The feedback

technique has been implemented with a third order, 3-bit

delta-sigma modulator for a low power radio receiver, in a

65 nm CMOS process, where it occupies an... (More)
The performance of continuous time deltasigma

modulators is limited by their large sensitivity to

feedback pulse-width variations caused by clock jitter in

their feedback DACs. To mitigate that effect, a dual switched-

capacitor-resistor feedback DAC technique is proposed.

The architecture has the additional benefit of

reducing the typically high switched-capacitor-resistor

DAC output peak currents, resulting in reduced slew-rate

requirements for the loop-filter integrators. The feedback

technique has been implemented with a third order, 3-bit

delta-sigma modulator for a low power radio receiver, in a

65 nm CMOS process, where it occupies an area of

0.17 mm2. It achieves an SNDR of 70 dB over a 125 kHz

bandwidth with an oversampling ratio of 16. The power

consumption is 380 lW from a 900 mV supply. (Less)
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Contribution to journal
publication status
published
subject
in
Analog Integrated Circuits and Signal Processing
publisher
Springer
external identifiers
  • wos:000312769900004
  • scopus:84871819399
ISSN
0925-1030
DOI
10.1007/s10470-012-9960-2
language
English
LU publication?
yes
id
05d9de63-baa0-4a93-bac2-269f94794c7c (old id 3130312)
date added to LUP
2012-10-17 14:11:15
date last changed
2017-08-27 04:33:06
@article{05d9de63-baa0-4a93-bac2-269f94794c7c,
  abstract     = {The performance of continuous time deltasigma<br/><br>
modulators is limited by their large sensitivity to<br/><br>
feedback pulse-width variations caused by clock jitter in<br/><br>
their feedback DACs. To mitigate that effect, a dual switched-<br/><br>
capacitor-resistor feedback DAC technique is proposed.<br/><br>
The architecture has the additional benefit of<br/><br>
reducing the typically high switched-capacitor-resistor<br/><br>
DAC output peak currents, resulting in reduced slew-rate<br/><br>
requirements for the loop-filter integrators. The feedback<br/><br>
technique has been implemented with a third order, 3-bit<br/><br>
delta-sigma modulator for a low power radio receiver, in a<br/><br>
65 nm CMOS process, where it occupies an area of<br/><br>
0.17 mm2. It achieves an SNDR of 70 dB over a 125 kHz<br/><br>
bandwidth with an oversampling ratio of 16. The power<br/><br>
consumption is 380 lW from a 900 mV supply.},
  author       = {Radjen, Dejan and Andersson, Martin and Sundström, Lars and Andreani, Pietro},
  issn         = {0925-1030},
  language     = {eng},
  publisher    = {Springer},
  series       = {Analog Integrated Circuits and Signal Processing},
  title        = {A Continuous Time Delta-Sigma Modulator with Reduced Clock Jitter Sensitivity through DSCR Feedback},
  url          = {http://dx.doi.org/10.1007/s10470-012-9960-2},
  year         = {2012},
}