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A 100-fJ/cycle Sub-VT Decimation Filter Chain in 65 nm CMOS

Sherazi, Syed Muhammad Yasser LU ; Nilsson, Peter LU ; Sjöland, Henrik LU and Rodrigues, Joachim LU (2012) IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2012 In [Host publication title missing]
Abstract
Measurements of a sub-threshold (sub-VT) decimation

filter, composed of four half band digital (HBD) filters in

65 nm CMOS are presented. Different unfolded architectures are

analyzed and implemented to combat speed degradation. The

architectures are analyzed for throughput and energy efficiency

over several threshold options. Reliability in the sub-VT domain

is analyzed by Monte-Carlo simulations. The simulation results

are validated by measurements and demonstrate that low-power

standard threshold logic (LP-SVT) and different architectural

flavors are suitable for a low-power implementation. Silicon

measurements prove functionality down to 350mV... (More)
Measurements of a sub-threshold (sub-VT) decimation

filter, composed of four half band digital (HBD) filters in

65 nm CMOS are presented. Different unfolded architectures are

analyzed and implemented to combat speed degradation. The

architectures are analyzed for throughput and energy efficiency

over several threshold options. Reliability in the sub-VT domain

is analyzed by Monte-Carlo simulations. The simulation results

are validated by measurements and demonstrate that low-power

standard threshold logic (LP-SVT) and different architectural

flavors are suitable for a low-power implementation. Silicon

measurements prove functionality down to 350mV supply, with

a maximum clock frequency of 500 kHz, having an energy

dissipation of 102 fJ/cycle. (Less)
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
in press
subject
keywords
energy dissipation, measurements, sub-threshold, half band digital (HBD) filters, 65 nm CMOS, and architectures.
in
[Host publication title missing]
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2012
project
EIT_UPD Wireless Communication for Ultra Portable Devices
language
English
LU publication?
yes
id
735747da-31f6-49ad-85ba-ff05edd0a26e (old id 3166941)
date added to LUP
2012-11-14 12:18:04
date last changed
2016-04-16 09:15:30
@inproceedings{735747da-31f6-49ad-85ba-ff05edd0a26e,
  abstract     = {Measurements of a sub-threshold (sub-VT) decimation<br/><br>
filter, composed of four half band digital (HBD) filters in<br/><br>
65 nm CMOS are presented. Different unfolded architectures are<br/><br>
analyzed and implemented to combat speed degradation. The<br/><br>
architectures are analyzed for throughput and energy efficiency<br/><br>
over several threshold options. Reliability in the sub-VT domain<br/><br>
is analyzed by Monte-Carlo simulations. The simulation results<br/><br>
are validated by measurements and demonstrate that low-power<br/><br>
standard threshold logic (LP-SVT) and different architectural<br/><br>
flavors are suitable for a low-power implementation. Silicon<br/><br>
measurements prove functionality down to 350mV supply, with<br/><br>
a maximum clock frequency of 500 kHz, having an energy<br/><br>
dissipation of 102 fJ/cycle.},
  author       = {Sherazi, Syed Muhammad Yasser and Nilsson, Peter and Sjöland, Henrik and Rodrigues, Joachim},
  booktitle    = {[Host publication title missing]},
  keyword      = {energy dissipation,measurements,sub-threshold,half band digital (HBD) filters,65 nm CMOS,and architectures.},
  language     = {eng},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  title        = {A 100-fJ/cycle Sub-VT Decimation Filter Chain in 65 nm CMOS},
  year         = {2012},
}