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Fabrication of Tunnel FETs demonstrating sub-thermal subthreshold slope

Krishnaraja, Abinaya LU ; Svensson, Johannes LU ; Lind, Erik LU and Wernersson, Lars-Erik LU (2019) 21th International Vacuum Congress
Abstract
Tunnel Field Effect Transistor (TFET), based on band-to-band tunneling, overcomes the thermal limit (subthreshold slope (S) > 60 mV/decade) of the MOSFETs by filtering the high-energy Fermi tail, thereby allowing a substantial reduction of supply voltage and power consumption. Despite the steep slope behavior, TFETs can suffer from ambipolarity wherein carriers tunnel into the channel at both high positive and negative gate voltages. In this work, we demonstrate the fabrication of InAs/InGaAsSb/GaSb vertical nanowire TFET devices and present experimental data showcasing suppressed ambipolarity and a minimum S = 39 mV/decade at Vds=0.05V. The nanowires were grown using MOVPE where the 100nm long InAs drain was n-doped with TESn followed... (More)
Tunnel Field Effect Transistor (TFET), based on band-to-band tunneling, overcomes the thermal limit (subthreshold slope (S) > 60 mV/decade) of the MOSFETs by filtering the high-energy Fermi tail, thereby allowing a substantial reduction of supply voltage and power consumption. Despite the steep slope behavior, TFETs can suffer from ambipolarity wherein carriers tunnel into the channel at both high positive and negative gate voltages. In this work, we demonstrate the fabrication of InAs/InGaAsSb/GaSb vertical nanowire TFET devices and present experimental data showcasing suppressed ambipolarity and a minimum S = 39 mV/decade at Vds=0.05V. The nanowires were grown using MOVPE where the 100nm long InAs drain was n-doped with TESn followed by a 100nm undoped InAs channel and a 100nm/300nm DEZn doped InGaAsSb/GaSb source. After growth, the InAs was selectively digitally etched using citric acid to reduce the channel diameter from 40nm to 25nm. The electrostatics was improved, compared to our previously reported devices, with a gate stack of ALD bilayer of 1nm/3nm Al2O3/HfO2 (EOT~1nm) followed by 30nm sputtered W. To decrease the ambipolar conduction, a gate-drain underlap of approximately 20nm was used which widens the tunnel barrier at the drain junction. Since the gate length is defined by the bottom spacer thickness in vertical transistors, the underlap provides a shorter gate positioned close to the source-channel junction. Thus the new process scheme has improved the slope and reduced the OFF current by one order of magnitude compared to our previous devices [1].


[1] E. Memisevic et al., IEEE Trans.ElectronDevices,vol.64,4746–4751, 2017.
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Contribution to conference
publication status
published
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conference name
21th International Vacuum Congress
conference location
Malmö, Sweden
conference dates
2019-07-01 - 2019-07-05
language
English
LU publication?
yes
id
318b3739-b54d-4827-b7e3-9b7c537766aa
alternative location
https://mkon.nu/RC_Data_FMS/Empire_data/files/file/All%20Poster%20Abstracts.pdf
date added to LUP
2019-10-15 14:49:25
date last changed
2019-10-16 16:21:26
@misc{318b3739-b54d-4827-b7e3-9b7c537766aa,
  abstract     = {Tunnel Field Effect Transistor (TFET), based on band-to-band tunneling, overcomes the thermal limit (subthreshold slope (S) &gt; 60 mV/decade) of the MOSFETs by filtering the high-energy Fermi tail, thereby allowing a substantial reduction of supply voltage and power consumption. Despite the steep slope behavior, TFETs can suffer from ambipolarity wherein carriers tunnel into the channel at both high positive and negative gate voltages. In this work, we demonstrate the fabrication of InAs/InGaAsSb/GaSb vertical nanowire TFET devices and present experimental data showcasing suppressed ambipolarity and a minimum S = 39 mV/decade at Vds=0.05V. The nanowires were grown using MOVPE where the 100nm long InAs drain was n-doped with TESn followed by a 100nm undoped InAs channel and a 100nm/300nm DEZn doped InGaAsSb/GaSb source. After growth, the InAs was selectively digitally etched using citric acid to reduce the channel diameter from 40nm to 25nm. The electrostatics was improved, compared to our previously reported devices, with a gate stack of ALD bilayer of 1nm/3nm Al2O3/HfO2 (EOT~1nm) followed by 30nm sputtered W. To decrease the ambipolar conduction, a gate-drain underlap of approximately 20nm was used which widens the tunnel barrier at the drain junction. Since the gate length is defined by the bottom spacer thickness in vertical transistors, the underlap provides a shorter gate positioned close to the source-channel junction. Thus the new process scheme has improved the slope and reduced the OFF current by one order of magnitude compared to our previous devices [1].<br>
 <br>
 <br>
[1] E. Memisevic et al., IEEE Trans.ElectronDevices,vol.64,4746–4751, 2017.<br>
 },
  author       = {Krishnaraja, Abinaya and Svensson, Johannes and Lind, Erik and Wernersson, Lars-Erik},
  language     = {eng},
  location     = {Malmö, Sweden},
  month        = {07},
  title        = {Fabrication of Tunnel FETs demonstrating sub-thermal subthreshold slope},
  year         = {2019},
}