Test Scheduling and Test Access Optimization for Core-Based 3D Stacked ICs with Through-Silicon Vias: poster
(2011) IEEE European Test Symposium (ETS), 2011
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/4305344
- author
- Sengupta, Breeta LU ; Ingelsson, Urban and Larsson, Erik LU
- organization
- publishing date
- 2011
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- host publication
- European Test Symposium (ETS11), Trondheim, Norway, May 23-27, 2011., 2011
- conference name
- IEEE European Test Symposium (ETS), 2011
- conference location
- Trondheim, Norway
- conference dates
- 2011-05-23 - 2011-05-27
- language
- English
- LU publication?
- no
- id
- 66253d7d-4b1d-4b5e-bc76-67058e367f2b (old id 4305344)
- date added to LUP
- 2016-04-04 14:04:01
- date last changed
- 2020-06-10 15:36:47
@inproceedings{66253d7d-4b1d-4b5e-bc76-67058e367f2b, author = {{Sengupta, Breeta and Ingelsson, Urban and Larsson, Erik}}, booktitle = {{European Test Symposium (ETS11), Trondheim, Norway, May 23-27, 2011., 2011}}, language = {{eng}}, title = {{Test Scheduling and Test Access Optimization for Core-Based 3D Stacked ICs with Through-Silicon Vias: poster}}, url = {{https://lup.lub.lu.se/search/files/80473997/4857408.pdf}}, year = {{2011}}, }