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A VLSI architecture of the square root algorithm for V-BLAST detection

Guo, Zhan and Nilsson, Peter LU (2006) In Journal of VLSI Signal Processing 44(3). p.219-230
Abstract
MIMO has been proposed as an extension to 3G and Wireless LANs. As an implementation scheme of MIMO systems, V-BLAST is suitable for the applications with very high data rates. The square root algorithm for V-BLAST detection is attractive to hardware implementations due to its low computational complexity and numerical stability. In this paper, the fixed-point implementation of the square root algorithm is analyzed, and a low complexity VLSI architecture is proposed. The proposed architecture is scalable for various configurations, and implemented for a 4 x 4 QPSK V-BLAST system in a 0.35 mu m CMOS technology. The chip core covers 9 mm(2) and 190 K gates. The detection throughput of the chip depends on the received symbol packet length.... (More)
MIMO has been proposed as an extension to 3G and Wireless LANs. As an implementation scheme of MIMO systems, V-BLAST is suitable for the applications with very high data rates. The square root algorithm for V-BLAST detection is attractive to hardware implementations due to its low computational complexity and numerical stability. In this paper, the fixed-point implementation of the square root algorithm is analyzed, and a low complexity VLSI architecture is proposed. The proposed architecture is scalable for various configurations, and implemented for a 4 x 4 QPSK V-BLAST system in a 0.35 mu m CMOS technology. The chip core covers 9 mm(2) and 190 K gates. The detection throughput of the chip depends on the received symbol packet length. When the packet length is larger than or equal to 100 bytes, it can achieve a maximal detection throughput of 128 similar to 160 Mb/s at a maximal clock frequency of 80 MHz. The core power consumption, measured at 2.7 V and room temperature, is about 608 mW for 160 Mb/s data rate at 80 MHz, and 81 mW for 20 Mb/s at 10 MHz. The proposed architecture is shown to meet the requirements for emerging MIMO applications, such as 3G HSDPA and IEEE 802.11n. (Less)
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author
organization
publishing date
type
Contribution to journal
publication status
published
subject
keywords
wireless LAN, CORDIC, fixed-point, square root algorithm, MIMO, BLAST, ASIC, VLSI, HSDPA, 3G
in
Journal of VLSI Signal Processing
volume
44
issue
3
pages
219 - 230
publisher
Springer
external identifiers
  • wos:000240538200002
  • scopus:33748690508
ISSN
0922-5773
DOI
10.1007/s11265-006-8536-8
language
English
LU publication?
yes
id
45b1365f-b93b-4e8c-93df-7e950c895e33 (old id 394024)
date added to LUP
2007-10-03 13:43:50
date last changed
2019-02-20 08:01:10
@article{45b1365f-b93b-4e8c-93df-7e950c895e33,
  abstract     = {MIMO has been proposed as an extension to 3G and Wireless LANs. As an implementation scheme of MIMO systems, V-BLAST is suitable for the applications with very high data rates. The square root algorithm for V-BLAST detection is attractive to hardware implementations due to its low computational complexity and numerical stability. In this paper, the fixed-point implementation of the square root algorithm is analyzed, and a low complexity VLSI architecture is proposed. The proposed architecture is scalable for various configurations, and implemented for a 4 x 4 QPSK V-BLAST system in a 0.35 mu m CMOS technology. The chip core covers 9 mm(2) and 190 K gates. The detection throughput of the chip depends on the received symbol packet length. When the packet length is larger than or equal to 100 bytes, it can achieve a maximal detection throughput of 128 similar to 160 Mb/s at a maximal clock frequency of 80 MHz. The core power consumption, measured at 2.7 V and room temperature, is about 608 mW for 160 Mb/s data rate at 80 MHz, and 81 mW for 20 Mb/s at 10 MHz. The proposed architecture is shown to meet the requirements for emerging MIMO applications, such as 3G HSDPA and IEEE 802.11n.},
  author       = {Guo, Zhan and Nilsson, Peter},
  issn         = {0922-5773},
  keyword      = {wireless LAN,CORDIC,fixed-point,square root algorithm,MIMO,BLAST,ASIC,VLSI,HSDPA,3G},
  language     = {eng},
  number       = {3},
  pages        = {219--230},
  publisher    = {Springer},
  series       = {Journal of VLSI Signal Processing},
  title        = {A VLSI architecture of the square root algorithm for V-BLAST detection},
  url          = {http://dx.doi.org/10.1007/s11265-006-8536-8},
  volume       = {44},
  year         = {2006},
}