An 11mW Continuous Time Delta-Sigma Modulator with 20 MHz Bandwidth in 65nm CMOS
(2014) IEEE International Symposium on Circuits and Systems (ISCAS), 2014 p.2337-2340- Abstract
- This paper presents a multi-bit, continuous time delta-sigma modulator with 20 MHz bandwidth implemented in 65nm CMOS for cellular communication. The modulator features a third order, single loop filter and a 4-bit internal quantizer operating at 640 MHz. The DACs are resistive for lower thermal noise compared to the current-steering DACs and nonreturn-to-zero DAC pulse is used to reduce the clock jitter sensitivity. The measured prototype consumes 11mW from a 1.2 V power supply, and achieves an SNDR/SFDR of 63.5dB/76dB.
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/5091488
- author
- Liu, Xiaodong LU ; Andersson, Mattias LU ; Anderson, Martin ; Sundstrom, Lars and Andreani, Pietro LU
- organization
- publishing date
- 2014
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- host publication
- 2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)
- pages
- 2337 - 2340
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- IEEE International Symposium on Circuits and Systems (ISCAS), 2014
- conference location
- Melbourne, Australia
- conference dates
- 2014-06-01 - 2014-06-05
- external identifiers
-
- wos:000346488600585
- scopus:84907389566
- ISSN
- 0271-4310
- 2158-1525
- language
- English
- LU publication?
- yes
- id
- 32c2ade9-4c91-449b-a11b-87c093263ce3 (old id 5091488)
- date added to LUP
- 2016-04-01 10:38:56
- date last changed
- 2025-01-14 19:51:21
@inproceedings{32c2ade9-4c91-449b-a11b-87c093263ce3, abstract = {{This paper presents a multi-bit, continuous time delta-sigma modulator with 20 MHz bandwidth implemented in 65nm CMOS for cellular communication. The modulator features a third order, single loop filter and a 4-bit internal quantizer operating at 640 MHz. The DACs are resistive for lower thermal noise compared to the current-steering DACs and nonreturn-to-zero DAC pulse is used to reduce the clock jitter sensitivity. The measured prototype consumes 11mW from a 1.2 V power supply, and achieves an SNDR/SFDR of 63.5dB/76dB.}}, author = {{Liu, Xiaodong and Andersson, Mattias and Anderson, Martin and Sundstrom, Lars and Andreani, Pietro}}, booktitle = {{2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)}}, issn = {{0271-4310}}, language = {{eng}}, pages = {{2337--2340}}, publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}}, title = {{An 11mW Continuous Time Delta-Sigma Modulator with 20 MHz Bandwidth in 65nm CMOS}}, year = {{2014}}, }