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A 2.7-6.1 GHz CMOS local oscillator based on frequency multiplication by 3/2

Bevilacqua, Andrea and Andreani, Pietro LU (2013) In Analog Integrated Circuits and Signal Processing 74(1). p.11-20
Abstract
Frequency multiplication by 3/2 is proposed as a means to expand the frequency generation capabilities of a single LC VCO. Fractional frequency multiplication is obtained by cascading a broadband injection locked modulo-two divider and a multiply-by-three circuit based on edge combining. The proposed solution is inductorless, thus very compact. It allows the generation of all frequencies from 2.7 to 6.1 GHz with a performance suitable for cellular standards. It shows a phase noise floor below -150 dBc/Hz and a spurious level below -35 dBc. The multiplier by 3/2 consumes 5 mA and the VCO draws 10 mA from a 1.2 V supply. The additional power consumption due to the multiplier trades with the small area penalty and the flexibility of this... (More)
Frequency multiplication by 3/2 is proposed as a means to expand the frequency generation capabilities of a single LC VCO. Fractional frequency multiplication is obtained by cascading a broadband injection locked modulo-two divider and a multiply-by-three circuit based on edge combining. The proposed solution is inductorless, thus very compact. It allows the generation of all frequencies from 2.7 to 6.1 GHz with a performance suitable for cellular standards. It shows a phase noise floor below -150 dBc/Hz and a spurious level below -35 dBc. The multiplier by 3/2 consumes 5 mA and the VCO draws 10 mA from a 1.2 V supply. The additional power consumption due to the multiplier trades with the small area penalty and the flexibility of this solution, compared to the use of multiple LC VCOs. (Less)
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author
and
organization
publishing date
type
Contribution to journal
publication status
published
subject
keywords
Voltage controlled oscillator, Injection locking, Fractional frequency, multiplier, Edge combining
in
Analog Integrated Circuits and Signal Processing
volume
74
issue
1
pages
11 - 20
publisher
Springer
external identifiers
  • wos:000312769900003
  • scopus:84871759093
ISSN
0925-1030
DOI
10.1007/s10470-012-9892-x
language
English
LU publication?
yes
id
53c24822-8f25-44d2-8924-3333d1244243 (old id 3481421)
date added to LUP
2016-04-01 13:15:18
date last changed
2022-01-27 18:07:47
@article{53c24822-8f25-44d2-8924-3333d1244243,
  abstract     = {{Frequency multiplication by 3/2 is proposed as a means to expand the frequency generation capabilities of a single LC VCO. Fractional frequency multiplication is obtained by cascading a broadband injection locked modulo-two divider and a multiply-by-three circuit based on edge combining. The proposed solution is inductorless, thus very compact. It allows the generation of all frequencies from 2.7 to 6.1 GHz with a performance suitable for cellular standards. It shows a phase noise floor below -150 dBc/Hz and a spurious level below -35 dBc. The multiplier by 3/2 consumes 5 mA and the VCO draws 10 mA from a 1.2 V supply. The additional power consumption due to the multiplier trades with the small area penalty and the flexibility of this solution, compared to the use of multiple LC VCOs.}},
  author       = {{Bevilacqua, Andrea and Andreani, Pietro}},
  issn         = {{0925-1030}},
  keywords     = {{Voltage controlled oscillator; Injection locking; Fractional frequency; multiplier; Edge combining}},
  language     = {{eng}},
  number       = {{1}},
  pages        = {{11--20}},
  publisher    = {{Springer}},
  series       = {{Analog Integrated Circuits and Signal Processing}},
  title        = {{A 2.7-6.1 GHz CMOS local oscillator based on frequency multiplication by 3/2}},
  url          = {{http://dx.doi.org/10.1007/s10470-012-9892-x}},
  doi          = {{10.1007/s10470-012-9892-x}},
  volume       = {{74}},
  year         = {{2013}},
}