A non-feedback multiphase clock generator using direct interpolation
(2002) 2002 45th Midwest Symposium on Circuits and Systems 1. p.340-343- Abstract
- This paper presents a new multiphase clock generator using direct interpolators. No feedback loop is required. A single-stage direct interpolation architecture is proposed. A 1/4 frequency divider and a short-circuit current suppression interpolator are developed to achieve the precise interpolation. The circuit was fabricated in a standard 0.35μm, 3.3V CMOS process. The multiphase clock generator can operate in a wide range of input clock frequencies from 500 MHz to 1 GHz.
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/610653
- author
- Lixin, Yang LU ; Yijun, Zhou LU and Yuan, Jiren LU
- organization
- publishing date
- 2002
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- keywords
- Multiphase clock generators
- host publication
- 2002 45th Midwest Symposium on Circuits and Systems, vol 1, Conference Proceedings
- volume
- 1
- pages
- 340 - 343
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- 2002 45th Midwest Symposium on Circuits and Systems
- conference location
- Tulsa, OK, United States
- conference dates
- 2002-08-04 - 2002-08-07
- external identifiers
-
- wos:000181336700087
- other:CODEN: MSCSDL
- scopus:0036979454
- ISBN
- 0-7803-7523-8
- language
- English
- LU publication?
- yes
- id
- 540ceb2c-ebd7-431b-aced-16074b9efc7c (old id 610653)
- alternative location
- http://ieeexplore.ieee.org/iel5/8452/26619/01187226.pdf
- date added to LUP
- 2016-04-04 10:15:20
- date last changed
- 2025-10-14 11:12:39
@inproceedings{540ceb2c-ebd7-431b-aced-16074b9efc7c,
abstract = {{This paper presents a new multiphase clock generator using direct interpolators. No feedback loop is required. A single-stage direct interpolation architecture is proposed. A 1/4 frequency divider and a short-circuit current suppression interpolator are developed to achieve the precise interpolation. The circuit was fabricated in a standard 0.35μm, 3.3V CMOS process. The multiphase clock generator can operate in a wide range of input clock frequencies from 500 MHz to 1 GHz.}},
author = {{Lixin, Yang and Yijun, Zhou and Yuan, Jiren}},
booktitle = {{2002 45th Midwest Symposium on Circuits and Systems, vol 1, Conference Proceedings}},
isbn = {{0-7803-7523-8}},
keywords = {{Multiphase clock generators}},
language = {{eng}},
pages = {{340--343}},
publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
title = {{A non-feedback multiphase clock generator using direct interpolation}},
url = {{http://ieeexplore.ieee.org/iel5/8452/26619/01187226.pdf}},
volume = {{1}},
year = {{2002}},
}