Yang Lixin (Former)

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2004
Mark A single-stage direct interpolation multiphase clock generator with phase error averaging
Lixin, Yang ^LU and Yuan, Jiren ^LU (2004) In Analog Integrated Circuits and Signal Processing 38(1). p.17-26
- Contribution to journal › Article
2003
Mark An arbitrarily skewable multiphase clock generator combining direct interpolation with phase error average
Lixin, Yang ^LU and Yuan, Jiren ^LU (2003) Proceedings of the 2003 IEEE International Symposium on Circuits and Systems 1. p.645-648
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
2002
Mark A non-feedback multiphase clock generator
Lixin, Yang ^LU ; Yijun, Zhou ^LU and Yuan, Jiren ^LU (2002) 2002 IEEE International Symposium on Circuits and Systems p.389-392
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
Mark A non-feedback multiphase clock generator using direct interpolation
Lixin, Yang ^LU ; Yijun, Zhou ^LU and Yuan, Jiren ^LU (2002) 2002 45th Midwest Symposium on Circuits and Systems 1. p.340-343
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
Mark A single-stage direct interpolation multiphase clock generator with phase error average
Lixin, Yang ^LU and Yuan, Jiren ^LU (2002) Norchip Conference, 2002 p.297-302
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding