Advanced

Reducing ambipolar off-state leakage currents in III-V vertical nanowire tunnel FETs using gate-drain underlap

Krishnaraja, Abinaya LU ; Svensson, Johannes LU ; Lind, Erik LU and Wernersson, Lars-Erik LU (2019) In Applied Physics Letters 115(14).
Abstract
Tunnel Field-Effect Transistors (TFETs) are an emerging alternative to CMOS for ultralow power and neuromorphic applications. The off current (Ioff) and, hence, the subthreshold swing (S) in these devices are limited by ambipolarity, which degrades its capabilities in complementary circuits. Here, we investigate experimentally vertical InAs/InGaAsSb/GaSb nanowire TFETs with gate-drain underlap as a potential solution to avoid ambipolarity and study the temperature dependence of the tunneling current. We compare two different TFET designs, one with an underlap between the gate and drain and the other with an overlap. The introduction of a 25-nm-long underlap region reduced the minimum achievable current Imin from 92 pA/μm to 23 pA/μm by... (More)
Tunnel Field-Effect Transistors (TFETs) are an emerging alternative to CMOS for ultralow power and neuromorphic applications. The off current (Ioff) and, hence, the subthreshold swing (S) in these devices are limited by ambipolarity, which degrades its capabilities in complementary circuits. Here, we investigate experimentally vertical InAs/InGaAsSb/GaSb nanowire TFETs with gate-drain underlap as a potential solution to avoid ambipolarity and study the temperature dependence of the tunneling current. We compare two different TFET designs, one with an underlap between the gate and drain and the other with an overlap. The introduction of a 25-nm-long underlap region reduced the minimum achievable current Imin from 92 pA/μm to 23 pA/μm by suppressing the ambipolarity and simultaneously improved the minimum S at room temperature from 46 mV/dec to 41 mV/dec at Vds = 0.1 V. We also observe a reduction in the measured on current (Ion) from 0.1 μA/μm in the overlapped device to 0.01 μA/μm in the underlapped device at a drain bias (Vds) = 0.1 V and Ioff = 1 nA/μm. Temperature dependent measurements reveal a potential barrier at the drain junction due to the ungated region at the underlap. We determine a barrier height of 63 meV at Vds = 0.1 V based on thermionic emission combined with a ballistic transport model. Thus, we conclude that gate placement on the drain side is crucial to obtain the low off-currents in TFETs required for ultralow power electronic applications but that the trade-off between Ion and Ioff has to be considered. (Less)
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Contribution to journal
publication status
published
subject
in
Applied Physics Letters
volume
115
issue
14
publisher
AIP Publishing LLC
external identifiers
  • scopus:85073257488
ISSN
1077-3118
DOI
10.1063/1.5115296
language
English
LU publication?
yes
id
5a6c704d-232a-4b23-9611-99109af56e48
date added to LUP
2019-10-11 17:54:30
date last changed
2019-10-29 05:57:40
@article{5a6c704d-232a-4b23-9611-99109af56e48,
  abstract     = {Tunnel Field-Effect Transistors (TFETs) are an emerging alternative to CMOS for ultralow power and neuromorphic applications. The off current (Ioff) and, hence, the subthreshold swing (S) in these devices are limited by ambipolarity, which degrades its capabilities in complementary circuits. Here, we investigate experimentally vertical InAs/InGaAsSb/GaSb nanowire TFETs with gate-drain underlap as a potential solution to avoid ambipolarity and study the temperature dependence of the tunneling current. We compare two different TFET designs, one with an underlap between the gate and drain and the other with an overlap. The introduction of a 25-nm-long underlap region reduced the minimum achievable current Imin from 92 pA/μm to 23 pA/μm by suppressing the ambipolarity and simultaneously improved the minimum S at room temperature from 46 mV/dec to 41 mV/dec at Vds = 0.1 V. We also observe a reduction in the measured on current (Ion) from 0.1 μA/μm in the overlapped device to 0.01 μA/μm in the underlapped device at a drain bias (Vds) = 0.1 V and Ioff = 1 nA/μm. Temperature dependent measurements reveal a potential barrier at the drain junction due to the ungated region at the underlap. We determine a barrier height of 63 meV at Vds = 0.1 V based on thermionic emission combined with a ballistic transport model. Thus, we conclude that gate placement on the drain side is crucial to obtain the low off-currents in TFETs required for ultralow power electronic applications but that the trade-off between Ion and Ioff has to be considered.},
  articleno    = {143505},
  author       = {Krishnaraja, Abinaya and Svensson, Johannes and Lind, Erik and Wernersson, Lars-Erik},
  issn         = {1077-3118},
  language     = {eng},
  month        = {10},
  number       = {14},
  publisher    = {AIP Publishing LLC},
  series       = {Applied Physics Letters},
  title        = {Reducing ambipolar off-state leakage currents in III-V vertical nanowire tunnel FETs using gate-drain underlap},
  url          = {http://dx.doi.org/10.1063/1.5115296},
  volume       = {115},
  year         = {2019},
}