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Reconfigurable multi-access pattern vector memory for real-time orb feature extraction

Ferreira, Lucas LU ; Malkowsky, Steffen LU ; Persson, Patrik LU orcid ; Aström, Karl LU orcid and Liu, Liang LU orcid (2021) 53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021 In Proceedings - IEEE International Symposium on Circuits and Systems 2021-May.
Abstract

This work presents an on-chip memory subsystem envisioned for real-time applications performing Oriented FAST and Rotated Brief (ORB) feature extraction for Simultaneous Localization and Mapping (SLAM) systems. For autonomous navigation of battery-powered devices, feature-based SLAM is a computationally frugal alternative to direct methods. This paper thoroughly analyses ORB multiple memory access patterns, exploring possible systematic parallelism and hardware-biased algorithmic enhancements, alleviating requirements on bandwidth and reducing redundant accesses. Enabling those, a suitable multi-bank parallel memory featuring run-time reconfigurable address generation, image allotment, and close-to-memory data-shuffling is proposed. As... (More)

This work presents an on-chip memory subsystem envisioned for real-time applications performing Oriented FAST and Rotated Brief (ORB) feature extraction for Simultaneous Localization and Mapping (SLAM) systems. For autonomous navigation of battery-powered devices, feature-based SLAM is a computationally frugal alternative to direct methods. This paper thoroughly analyses ORB multiple memory access patterns, exploring possible systematic parallelism and hardware-biased algorithmic enhancements, alleviating requirements on bandwidth and reducing redundant accesses. Enabling those, a suitable multi-bank parallel memory featuring run-time reconfigurable address generation, image allotment, and close-to-memory data-shuffling is proposed. As case study, a 30 Frames-Per-Second (FPS) VGA-resolution ORB-capable 8-bank memory is evaluated using 22 FDX technology, running at 909 MHz, with a negligible area overhead of 0.3%, reducing operand accesses between 54 − 160× relative to Sudoku-like and scalar memories.

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Please use this url to cite or link to this publication:
author
; ; ; and
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
Feature extraction, ORB, Programmable multiple memory access patterns, Vision-based SLAM
host publication
2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings
series title
Proceedings - IEEE International Symposium on Circuits and Systems
volume
2021-May
article number
9401698
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
conference name
53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021
conference location
Daegu, Korea, Republic of
conference dates
2021-05-22 - 2021-05-28
external identifiers
  • scopus:85108985865
ISSN
0271-4310
ISBN
9781728192017
DOI
10.1109/ISCAS51556.2021.09401698
language
English
LU publication?
yes
id
601af2cd-1ad5-4519-8381-0b10f6f35da4
date added to LUP
2021-08-19 11:28:20
date last changed
2024-03-23 07:59:17
@inproceedings{601af2cd-1ad5-4519-8381-0b10f6f35da4,
  abstract     = {{<p>This work presents an on-chip memory subsystem envisioned for real-time applications performing Oriented FAST and Rotated Brief (ORB) feature extraction for Simultaneous Localization and Mapping (SLAM) systems. For autonomous navigation of battery-powered devices, feature-based SLAM is a computationally frugal alternative to direct methods. This paper thoroughly analyses ORB multiple memory access patterns, exploring possible systematic parallelism and hardware-biased algorithmic enhancements, alleviating requirements on bandwidth and reducing redundant accesses. Enabling those, a suitable multi-bank parallel memory featuring run-time reconfigurable address generation, image allotment, and close-to-memory data-shuffling is proposed. As case study, a 30 Frames-Per-Second (FPS) VGA-resolution ORB-capable 8-bank memory is evaluated using 22 FDX technology, running at 909 MHz, with a negligible area overhead of 0.3%, reducing operand accesses between 54 − 160× relative to Sudoku-like and scalar memories.</p>}},
  author       = {{Ferreira, Lucas and Malkowsky, Steffen and Persson, Patrik and Aström, Karl and Liu, Liang}},
  booktitle    = {{2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings}},
  isbn         = {{9781728192017}},
  issn         = {{0271-4310}},
  keywords     = {{Feature extraction; ORB; Programmable multiple memory access patterns; Vision-based SLAM}},
  language     = {{eng}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  series       = {{Proceedings - IEEE International Symposium on Circuits and Systems}},
  title        = {{Reconfigurable multi-access pattern vector memory for real-time orb feature extraction}},
  url          = {{http://dx.doi.org/10.1109/ISCAS51556.2021.09401698}},
  doi          = {{10.1109/ISCAS51556.2021.09401698}},
  volume       = {{2021-May}},
  year         = {{2021}},
}