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A configurable divider using digit recurrence

Berkeman, Anders LU and Öwall, Viktor LU (2003) IEEE International Symposium on Circuits and Systems (ISCAS '03), 2003 In Proceedings - IEEE International Symposium on Circuits and Systems 5. p.333-336
Abstract
The division operation is essential in many digital signal processing algorithms. For a hardware implementation, the requirements and constraints on the divider circuit differ significantly with different applications. Therefore, it is not possible to design one divider component having optimal performance and cost for all target applications. Instead, the presented divider has a modular architecture, based on instantiation of small efficient divider sub-blocks. The configuration of the divider architecture is set by a number of parameters controlling wordlength, number of quotient bits, number of clock cycles per operation, and fixed or floating point operation. Digit recurrence algorithms with carry save arithmetic and on-the-fly two's... (More)
The division operation is essential in many digital signal processing algorithms. For a hardware implementation, the requirements and constraints on the divider circuit differ significantly with different applications. Therefore, it is not possible to design one divider component having optimal performance and cost for all target applications. Instead, the presented divider has a modular architecture, based on instantiation of small efficient divider sub-blocks. The configuration of the divider architecture is set by a number of parameters controlling wordlength, number of quotient bits, number of clock cycles per operation, and fixed or floating point operation. Digit recurrence algorithms with carry save arithmetic and on-the-fly two's complement output quotient conversion are used to make the sub-blocks small, fast and power efficient, The modularity gives the designer freedom to elaborate different parameters to explore the design space. Two applications using the proposed divider are presented. Furthermore, an example divider circuit has been fabricated and performance measurements are included. (Less)
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
Divider circuits
in
Proceedings - IEEE International Symposium on Circuits and Systems
volume
5
pages
4 pages
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
IEEE International Symposium on Circuits and Systems (ISCAS '03), 2003
external identifiers
  • wos:000184904800084
  • scopus:0038082037
ISSN
0271-4310
2158-1525
DOI
language
English
LU publication?
yes
id
ef0d0b8f-239b-4322-b075-17bf42390c4d (old id 611889)
date added to LUP
2007-11-28 10:10:16
date last changed
2018-05-29 09:58:08
@inproceedings{ef0d0b8f-239b-4322-b075-17bf42390c4d,
  abstract     = {The division operation is essential in many digital signal processing algorithms. For a hardware implementation, the requirements and constraints on the divider circuit differ significantly with different applications. Therefore, it is not possible to design one divider component having optimal performance and cost for all target applications. Instead, the presented divider has a modular architecture, based on instantiation of small efficient divider sub-blocks. The configuration of the divider architecture is set by a number of parameters controlling wordlength, number of quotient bits, number of clock cycles per operation, and fixed or floating point operation. Digit recurrence algorithms with carry save arithmetic and on-the-fly two's complement output quotient conversion are used to make the sub-blocks small, fast and power efficient, The modularity gives the designer freedom to elaborate different parameters to explore the design space. Two applications using the proposed divider are presented. Furthermore, an example divider circuit has been fabricated and performance measurements are included.},
  author       = {Berkeman, Anders and Öwall, Viktor},
  booktitle    = {Proceedings - IEEE International Symposium on Circuits and Systems},
  issn         = {0271-4310},
  keyword      = {Divider circuits},
  language     = {eng},
  pages        = {333--336},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  title        = {A configurable divider using digit recurrence},
  url          = {http://dx.doi.org/},
  volume       = {5},
  year         = {2003},
}