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A digitally controlled PLL for digital SOCs

Olsson, Thomas LU and Nilsson, Peter LU (2003) Proceedings of the 2003 IEEE International Symposium on Circuits and Systems In Proceedings - IEEE International Symposium on Circuits and Systems 5. p.437-440
Abstract
A fully integrated digitally controlled PLL used as a clock multiplying circuit is designed and fabricated. The PLL has no off-chip components and it is made from standard cells found in most digital standard cell libraries. It is therefore portable between processes as an IP-block. Using a 0.35 μm standard CMOS process and a 3.0 V supply, the PLL has a frequency range of 152 MHz to 366 MHz and occupies an on-chip area of about 0.07 mm<sup>2</sup>. In addition, the next version of this all-digital PLL is described in synthesizable VHDL-code, which simplifies digital system simulation and change of process. A new time-to-digital converter with simulated resolution of 250 ps is made for the next PLL.
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author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
Digital systems
in
Proceedings - IEEE International Symposium on Circuits and Systems
volume
5
pages
437 - 440
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
Proceedings of the 2003 IEEE International Symposium on Circuits and Systems
external identifiers
  • wos:000184904800110
  • other:CODEN: PICSDI
  • scopus:0038420044
ISSN
0271-4310
2158-1525
DOI
10.1109/ISCAS.2003.1206308
language
English
LU publication?
yes
id
84479eb2-3edd-4fbb-ae7b-c23f477ea889 (old id 612770)
date added to LUP
2007-11-30 15:38:06
date last changed
2018-05-29 11:10:17
@inproceedings{84479eb2-3edd-4fbb-ae7b-c23f477ea889,
  abstract     = {A fully integrated digitally controlled PLL used as a clock multiplying circuit is designed and fabricated. The PLL has no off-chip components and it is made from standard cells found in most digital standard cell libraries. It is therefore portable between processes as an IP-block. Using a 0.35 μm standard CMOS process and a 3.0 V supply, the PLL has a frequency range of 152 MHz to 366 MHz and occupies an on-chip area of about 0.07 mm&lt;sup&gt;2&lt;/sup&gt;. In addition, the next version of this all-digital PLL is described in synthesizable VHDL-code, which simplifies digital system simulation and change of process. A new time-to-digital converter with simulated resolution of 250 ps is made for the next PLL.},
  author       = {Olsson, Thomas and Nilsson, Peter},
  booktitle    = {Proceedings - IEEE International Symposium on Circuits and Systems},
  issn         = {0271-4310},
  keyword      = {Digital systems},
  language     = {eng},
  pages        = {437--440},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  title        = {A digitally controlled PLL for digital SOCs},
  url          = {http://dx.doi.org/10.1109/ISCAS.2003.1206308},
  volume       = {5},
  year         = {2003},
}