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Wrap-gated InAs nanowire field-effect transistor

Wernersson, Lars-Erik LU ; Bryllert, Tomas LU ; Lind, Erik LU and Samuelson, Lars LU (2005) International Electron Devices Meeting 2005 In International Electron Devices Meeting 2005 p.273-276
Abstract
Field-effect transistors (FETs) based on semiconductor nanowires (Bryllert et al., 2005) have the potential to improve certain aspects of existing planar FET technologies. The possibility to form wrap-gates gives an efficient gate coupling resulting in reduced drain-induced barrier lowering. Furthermore, lateral strain relaxation allows a new freedom in combining materials in heterostructures, where materials with different lattice constants can be combined without defects (Bjork et al., 2002). Since the transistor channel, unlike the planar FETs, is vertical, heterostructures may be used to tailor the bandstructure along the direction of current flow. In this paper, we demonstrate a new technology to fabricate vertical nanowire FETs in a... (More)
Field-effect transistors (FETs) based on semiconductor nanowires (Bryllert et al., 2005) have the potential to improve certain aspects of existing planar FET technologies. The possibility to form wrap-gates gives an efficient gate coupling resulting in reduced drain-induced barrier lowering. Furthermore, lateral strain relaxation allows a new freedom in combining materials in heterostructures, where materials with different lattice constants can be combined without defects (Bjork et al., 2002). Since the transistor channel, unlike the planar FETs, is vertical, heterostructures may be used to tailor the bandstructure along the direction of current flow. In this paper, we demonstrate a new technology to fabricate vertical nanowire FETs in a process that almost exclusively relies on optical lithography and standard III-V processing techniques. We measure encouraging electrical data, including current saturation at V<sub>ds</sub> ≡ 0.15 V (for V<sub>g</sub> ≡ 0 V) and low voltage operation V<sub>th</sub> ≡ -0.15 V, and present opportunities to improve the device performance by heterostructure design (Less)
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
optical lithography, lattice constants, 0.15 V, InAs, heterostructures design, lateral strain relaxation, drain induced barrier lowering, gate coupling, semiconductor nanowires, wrap gated nanowire, field effect transistor
in
International Electron Devices Meeting 2005
pages
4 pages
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
International Electron Devices Meeting 2005
external identifiers
  • wos:000236225100061
  • scopus:33847714694
ISBN
0-7803-9268-X
DOI
10.1109/IEDM.2005.1609324
language
English
LU publication?
yes
id
852bf4b0-d921-40a7-9b86-0a3227d7766a (old id 616530)
date added to LUP
2007-11-25 17:38:14
date last changed
2017-03-26 04:34:31
@inproceedings{852bf4b0-d921-40a7-9b86-0a3227d7766a,
  abstract     = {Field-effect transistors (FETs) based on semiconductor nanowires (Bryllert et al., 2005) have the potential to improve certain aspects of existing planar FET technologies. The possibility to form wrap-gates gives an efficient gate coupling resulting in reduced drain-induced barrier lowering. Furthermore, lateral strain relaxation allows a new freedom in combining materials in heterostructures, where materials with different lattice constants can be combined without defects (Bjork et al., 2002). Since the transistor channel, unlike the planar FETs, is vertical, heterostructures may be used to tailor the bandstructure along the direction of current flow. In this paper, we demonstrate a new technology to fabricate vertical nanowire FETs in a process that almost exclusively relies on optical lithography and standard III-V processing techniques. We measure encouraging electrical data, including current saturation at V&lt;sub&gt;ds&lt;/sub&gt; ≡ 0.15 V (for V&lt;sub&gt;g&lt;/sub&gt; ≡ 0 V) and low voltage operation V&lt;sub&gt;th&lt;/sub&gt; ≡ -0.15 V, and present opportunities to improve the device performance by heterostructure design},
  author       = {Wernersson, Lars-Erik and Bryllert, Tomas and Lind, Erik and Samuelson, Lars},
  booktitle    = {International Electron Devices Meeting 2005},
  isbn         = {0-7803-9268-X},
  keyword      = {optical lithography,lattice constants,0.15 V,InAs,heterostructures design,lateral strain relaxation,drain induced barrier lowering,gate coupling,semiconductor nanowires,wrap gated nanowire,field effect transistor},
  language     = {eng},
  pages        = {273--276},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  title        = {Wrap-gated InAs nanowire field-effect transistor},
  url          = {http://dx.doi.org/10.1109/IEDM.2005.1609324},
  year         = {2005},
}