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A 10-bit 500-MS/s 124-mW subranging folding ADC in 0.13 μm CMOS

Chen, Cheng and Yuan, Jiren LU (2007) 2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007 In Proceedings - IEEE International Symposium on Circuits and Systems p.1709-1712
Abstract
A 10-bit two-step subranging folding analog-to-digital converter (ADC) that converts signal at 500 MSample/s is presented. Using dual-channel preprocessing blocks with distributed sample-and-hold circuits and two-stage amplifiers in which auto-zero calibration technique is employed, the proposed 10-bit ADC has a wide input bandwidth (>250MHz). The ADC consumes 124mW from a 1.2V power supply. The performance is verified by Sepctre simulation in a digital 0.13μm CMOS process. The chip occupies an active area of 0.54mm<sup>2</sup>. © 2007 IEEE.
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
Preprocessing blocks, Auto-zero calibration, Wide input bandwidth, Sepctre simulation
in
Proceedings - IEEE International Symposium on Circuits and Systems
pages
1709 - 1712
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007
external identifiers
  • wos:000251608402062
  • other:CODEN: PICSDI
  • scopus:34548817332
ISSN
2158-1525
0271-4310
DOI
10.1109/ISCAS.2007.377923
language
English
LU publication?
yes
id
ae0dc4e2-4210-4951-9f7e-13cefac6618d (old id 643301)
date added to LUP
2007-12-04 14:24:42
date last changed
2017-06-04 03:38:29
@inproceedings{ae0dc4e2-4210-4951-9f7e-13cefac6618d,
  abstract     = {A 10-bit two-step subranging folding analog-to-digital converter (ADC) that converts signal at 500 MSample/s is presented. Using dual-channel preprocessing blocks with distributed sample-and-hold circuits and two-stage amplifiers in which auto-zero calibration technique is employed, the proposed 10-bit ADC has a wide input bandwidth (&gt;250MHz). The ADC consumes 124mW from a 1.2V power supply. The performance is verified by Sepctre simulation in a digital 0.13μm CMOS process. The chip occupies an active area of 0.54mm&lt;sup&gt;2&lt;/sup&gt;. © 2007 IEEE.},
  author       = {Chen, Cheng and Yuan, Jiren},
  booktitle    = {Proceedings - IEEE International Symposium on Circuits and Systems},
  issn         = {2158-1525},
  keyword      = {Preprocessing blocks,Auto-zero calibration,Wide input bandwidth,Sepctre simulation},
  language     = {eng},
  pages        = {1709--1712},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  title        = {A 10-bit 500-MS/s 124-mW subranging folding ADC in 0.13 μm CMOS},
  url          = {http://dx.doi.org/10.1109/ISCAS.2007.377923},
  year         = {2007},
}