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InAs WRAP-gate nanowire transistors

Wernersson, Lars-Erik LU (2007) IPRM'07: IEEE 19th International Conference on Indium Phosphide and Related Materials In Conference Proceedings - International Conference on Indium Phosphide and Related Materials p.527-529
Abstract
InAs nanowire wrap-gate transistors have been fabricated in a vertical geometry using matrices of 11×11 nanowires. The fabrication process is based on conventional and scalable technologies that are adopted for the nanowire transistors. A SiN<sub>x</sub> layer is used as gate dielectric and a wrap-gate of 80 nm gate length is formed. These transistors show good DC characteristics with drive currents above 1 mA and a transconductance of 0.28 mS at V<sub>sd</sub>=0.5V. The transistors operate in depletion mode. © 2007 IEEE.
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
Drive currents, Nanowire transistors, WRAP-gate nanowire, Scalable technologies
in
Conference Proceedings - International Conference on Indium Phosphide and Related Materials
pages
527 - 529
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
IPRM'07: IEEE 19th International Conference on Indium Phosphide and Related Materials
external identifiers
  • wos:000248523100139
  • other:CODEN: CPRMEG
  • scopus:34748887765
ISSN
1092-8669
DOI
10.1109/ICIPRM.2007.381244
language
English
LU publication?
yes
id
de41eabd-8461-48a5-8cd9-4406660bd6fe (old id 643428)
date added to LUP
2007-12-04 10:59:38
date last changed
2017-01-01 07:03:48
@inproceedings{de41eabd-8461-48a5-8cd9-4406660bd6fe,
  abstract     = {InAs nanowire wrap-gate transistors have been fabricated in a vertical geometry using matrices of 11×11 nanowires. The fabrication process is based on conventional and scalable technologies that are adopted for the nanowire transistors. A SiN&lt;sub&gt;x&lt;/sub&gt; layer is used as gate dielectric and a wrap-gate of 80 nm gate length is formed. These transistors show good DC characteristics with drive currents above 1 mA and a transconductance of 0.28 mS at V&lt;sub&gt;sd&lt;/sub&gt;=0.5V. The transistors operate in depletion mode. © 2007 IEEE.},
  author       = {Wernersson, Lars-Erik},
  booktitle    = {Conference Proceedings - International Conference on Indium Phosphide and Related Materials},
  issn         = {1092-8669},
  keyword      = {Drive currents,Nanowire transistors,WRAP-gate nanowire,Scalable technologies},
  language     = {eng},
  pages        = {527--529},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  title        = {InAs WRAP-gate nanowire transistors},
  url          = {http://dx.doi.org/10.1109/ICIPRM.2007.381244},
  year         = {2007},
}