Advanced

Vertical InAs-Si gate-all-around tunnel FETs integrated on Si using selective epitaxy in nanotube templates

Cutaia, Davide; Moselund, Kirsten E.; Borg, Mattias LU ; Schmid, Heinz; Gignac, Lynne; Breslin, Chris M.; Karg, Siegfried; Uccelli, Emanuele and Riel, Heike (2015) In IEEE Journal of the Electron Devices Society 3(3). p.176-183
Abstract

In this paper, we introduce ${p -channel InAs-Si tunnel field-effect transistors (TFETs) fabricated using selective epitaxy in nanotube templates. We demonstrate the versatility of this approach, which enables III-V nanowire integration on Si substrates of any crystalline orientation. Electrical characterization of diodes and of TFETs fabricated using this method is presented; the TFETs exhibit a good overall performance with on-currents, ${I} -{\rm on of 6 μ A/ μ m ( $|V-{GS}| = |V-{DS}| = 1$ V) and a room-temperature subthreshold swing (SS) of $\sim 160$ mV/dec over at least three orders of magnitude in current. Temperature-dependent measurements indicate that SS is limited by traps. We demonstrate improved TFET ${I} -{\rm on... (More)

In this paper, we introduce ${p -channel InAs-Si tunnel field-effect transistors (TFETs) fabricated using selective epitaxy in nanotube templates. We demonstrate the versatility of this approach, which enables III-V nanowire integration on Si substrates of any crystalline orientation. Electrical characterization of diodes and of TFETs fabricated using this method is presented; the TFETs exhibit a good overall performance with on-currents, ${I} -{\rm on of 6 μ A/ μ m ( $|V-{GS}| = |V-{DS}| = 1$ V) and a room-temperature subthreshold swing (SS) of $\sim 160$ mV/dec over at least three orders of magnitude in current. Temperature-dependent measurements indicate that SS is limited by traps. We demonstrate improved TFET ${I} -{\rm on performance by 1-2 orders of magnitude by scaling the equivalent oxide thickness from 2.7 to 1.5 nm. Furthermore, a novel benchmarking scheme is proposed to allow the comparison of different TFET data found in literature despite the different measurement conditions used.

(Less)
Please use this url to cite or link to this publication:
author
publishing date
type
Contribution to journal
publication status
published
subject
keywords
heterojunctions, III-V semiconductor materials, low-power electronics., nanowires, tunnel diode, tunnel transistor
in
IEEE Journal of the Electron Devices Society
volume
3
issue
3
pages
8 pages
publisher
Institute of Electrical and Electronics Engineers Inc.
external identifiers
  • scopus:84928615074
DOI
10.1109/JEDS.2015.2388793
language
English
LU publication?
no
id
69590d03-0795-49a1-a183-6a09282a3596
date added to LUP
2016-04-20 10:31:10
date last changed
2017-08-27 06:15:52
@article{69590d03-0795-49a1-a183-6a09282a3596,
  abstract     = {<p>In this paper, we introduce ${p -channel InAs-Si tunnel field-effect transistors (TFETs) fabricated using selective epitaxy in nanotube templates. We demonstrate the versatility of this approach, which enables III-V nanowire integration on Si substrates of any crystalline orientation. Electrical characterization of diodes and of TFETs fabricated using this method is presented; the TFETs exhibit a good overall performance with on-currents, ${I} -{\rm on of 6 μ A/ μ m ( $|V-{GS}| = |V-{DS}| = 1$ V) and a room-temperature subthreshold swing (SS) of $\sim 160$ mV/dec over at least three orders of magnitude in current. Temperature-dependent measurements indicate that SS is limited by traps. We demonstrate improved TFET ${I} -{\rm on performance by 1-2 orders of magnitude by scaling the equivalent oxide thickness from 2.7 to 1.5 nm. Furthermore, a novel benchmarking scheme is proposed to allow the comparison of different TFET data found in literature despite the different measurement conditions used.</p>},
  articleno    = {7001544},
  author       = {Cutaia, Davide and Moselund, Kirsten E. and Borg, Mattias and Schmid, Heinz and Gignac, Lynne and Breslin, Chris M. and Karg, Siegfried and Uccelli, Emanuele and Riel, Heike},
  keyword      = {heterojunctions,III-V semiconductor materials,low-power electronics.,nanowires,tunnel diode,tunnel transistor},
  language     = {eng},
  month        = {05},
  number       = {3},
  pages        = {176--183},
  publisher    = {Institute of Electrical and Electronics Engineers Inc.},
  series       = {IEEE Journal of the Electron Devices Society},
  title        = {Vertical InAs-Si gate-all-around tunnel FETs integrated on Si using selective epitaxy in nanotube templates},
  url          = {http://dx.doi.org/10.1109/JEDS.2015.2388793},
  volume       = {3},
  year         = {2015},
}