Advanced

A low-power 2nd-order CT delta-sigma modulator with an asynchronous SAR quantizer

Radjen, Dejan LU ; Anderson, Martin; Sundstrom, Lars and Andreani, Pietro LU (2015) In Analog Integrated Circuits and Signal Processing 84(3). p.409-420
Abstract
This paper presents a low voltage continuous-time delta-sigma modulator (DSM) intended for the receiver of an ultra-low-power radio. The DSM features a 2nd-order loop filter implemented with a single operational amplifier to reduce the power consumption. Furthermore, a 4-bit quantizer is used to achieve high resolution while keeping the sampling frequency low. The quantizer is realized using the successive approximation register architecture with asynchronous control which is more power efficient than the commonly used flash architecture. The DSM has been implemented in a 65 nm CMOS process. Simulation results show a peak SNDR of 65 dB over a 500 kHz signal bandwidth. The DSM consumes 69 W from a 800 mV power supply.
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Contribution to journal
publication status
published
subject
keywords
Delta-sigma, Asynchronous SAR, Single operational amplifier, Low-power, Continuous time
in
Analog Integrated Circuits and Signal Processing
volume
84
issue
3
pages
409 - 420
publisher
Springer
external identifiers
  • wos:000359013100008
  • scopus:84938738633
ISSN
0925-1030
DOI
10.1007/s10470-015-0590-3
language
English
LU publication?
yes
id
5d6628e0-b1c4-464f-9a7c-2e8b945246f4 (old id 7975720)
date added to LUP
2015-09-25 10:45:17
date last changed
2017-04-02 03:55:53
@article{5d6628e0-b1c4-464f-9a7c-2e8b945246f4,
  abstract     = {This paper presents a low voltage continuous-time delta-sigma modulator (DSM) intended for the receiver of an ultra-low-power radio. The DSM features a 2nd-order loop filter implemented with a single operational amplifier to reduce the power consumption. Furthermore, a 4-bit quantizer is used to achieve high resolution while keeping the sampling frequency low. The quantizer is realized using the successive approximation register architecture with asynchronous control which is more power efficient than the commonly used flash architecture. The DSM has been implemented in a 65 nm CMOS process. Simulation results show a peak SNDR of 65 dB over a 500 kHz signal bandwidth. The DSM consumes 69 W from a 800 mV power supply.},
  author       = {Radjen, Dejan and Anderson, Martin and Sundstrom, Lars and Andreani, Pietro},
  issn         = {0925-1030},
  keyword      = {Delta-sigma,Asynchronous SAR,Single operational amplifier,Low-power,Continuous time},
  language     = {eng},
  number       = {3},
  pages        = {409--420},
  publisher    = {Springer},
  series       = {Analog Integrated Circuits and Signal Processing},
  title        = {A low-power 2nd-order CT delta-sigma modulator with an asynchronous SAR quantizer},
  url          = {http://dx.doi.org/10.1007/s10470-015-0590-3},
  volume       = {84},
  year         = {2015},
}