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An Experimental Study of Heterostructure Tunnel FET Nanowire Arrays : Digital and Analog Figures of Merit from 300K to 10K

Rosca, T.; Saeidi, A.; Memisevic, E. LU ; Wernersson, L. E. LU and Ionescu, A. M. (2019) 64th Annual IEEE International Electron Devices Meeting, IEDM 2018 2018. p.1-13
Abstract


In this work, we experimentally report the figures of merit of state-of-the-art heterostructure Tunnel Field-Effect-Transistor (TFET) arrays from room (300K) down to cryogenic temperature (10K) at supply voltages below 400mV. We demonstrate here, for the first time, that InAs/InGaAsSb/GaSb Nanowire (NW) TFETs are robust enough to maintain excellent figures of merit over a large temperature range even in devices with a large number arrayed nanowires (here, from 4 to 184 nanowires per device), accounting for technological variability. The investigated Tunnel FETs have temperature-independent min and average subthreshold swings of 45mV/dec/67mV/dec in large NW arrays, versus... (More)


In this work, we experimentally report the figures of merit of state-of-the-art heterostructure Tunnel Field-Effect-Transistor (TFET) arrays from room (300K) down to cryogenic temperature (10K) at supply voltages below 400mV. We demonstrate here, for the first time, that InAs/InGaAsSb/GaSb Nanowire (NW) TFETs are robust enough to maintain excellent figures of merit over a large temperature range even in devices with a large number arrayed nanowires (here, from 4 to 184 nanowires per device), accounting for technological variability. The investigated Tunnel FETs have temperature-independent min and average subthreshold swings of 45mV/dec/67mV/dec in large NW arrays, versus ∼36/45mV/dec in smaller arrays, once the trap-assisted tunneling is removed (from 150K down to 10K). In all NW arrays we observe improvement of the on-current and of maximum transconductance, gmax, at cryogenic temperatures, with very little dependence of temperature, from 150K to 10K. The paper reports that in the range 150K to 10K only band-to-band-tunneling dominates the analog figures of merit of Tunnel FETs; we measured transconductance efficiencincies higher than 60V
-1
for small arrays (breaking the limit of CMOS at RT) and close to 42V
-1
for large arrays, for supply volrages smaller than 100mV, offering the possibility to design future energy efficient readouts and analog-to-digital converters. In contrast with cryogenic MOSFETs, Tunnel FETs show almost no hysteresis (<24mV), steep transfer characteristics, are free of kinks in output characteristics, with a unique stability of the swing drift with T, and negligible threshold voltage drift in all arrays configurations.

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author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
host publication
2018 IEEE International Electron Devices Meeting, IEDM 2018
volume
2018
pages
1 - 13
publisher
Institute of Electrical and Electronics Engineers Inc.
conference name
64th Annual IEEE International Electron Devices Meeting, IEDM 2018
conference location
San Francisco, United States
conference dates
2018-12-01 - 2018-12-05
external identifiers
  • scopus:85061841486
ISBN
9781728119878
DOI
10.1109/IEDM.2018.8614665
language
English
LU publication?
yes
id
7f9b1633-19ff-4049-806f-cf1f3e72ff9a
date added to LUP
2019-03-04 08:36:27
date last changed
2019-03-27 04:39:35
@inproceedings{7f9b1633-19ff-4049-806f-cf1f3e72ff9a,
  abstract     = {<p><br>
                                                         In this work, we experimentally report the figures of merit of state-of-the-art heterostructure Tunnel Field-Effect-Transistor (TFET) arrays from room (300K) down to cryogenic temperature (10K) at supply voltages below 400mV. We demonstrate here, for the first time, that InAs/InGaAsSb/GaSb Nanowire (NW) TFETs are robust enough to maintain excellent figures of merit over a large temperature range even in devices with a large number arrayed nanowires (here, from 4 to 184 nanowires per device), accounting for technological variability. The investigated Tunnel FETs have temperature-independent min and average subthreshold swings of 45mV/dec/67mV/dec in large NW arrays, versus ∼36/45mV/dec in smaller arrays, once the trap-assisted tunneling is removed (from 150K down to 10K). In all NW arrays we observe improvement of the on-current and of maximum transconductance, gmax, at cryogenic temperatures, with very little dependence of temperature, from 150K to 10K. The paper reports that in the range 150K to 10K only band-to-band-tunneling dominates the analog figures of merit of Tunnel FETs; we measured transconductance efficiencincies higher than 60V                             <br>
                            <sup>-1</sup><br>
                                                          for small arrays (breaking the limit of CMOS at RT) and close to 42V                             <br>
                            <sup>-1</sup><br>
                                                          for large arrays, for supply volrages smaller than 100mV, offering the possibility to design future energy efficient readouts and analog-to-digital converters. In contrast with cryogenic MOSFETs, Tunnel FETs show almost no hysteresis (&lt;24mV), steep transfer characteristics, are free of kinks in output characteristics, with a unique stability of the swing drift with T, and negligible threshold voltage drift in all arrays configurations.                         <br>
                        </p>},
  author       = {Rosca, T. and Saeidi, A. and Memisevic, E. and Wernersson, L. E. and Ionescu, A. M.},
  isbn         = {9781728119878},
  language     = {eng},
  location     = {San Francisco, United States},
  month        = {01},
  pages        = {1--13},
  publisher    = {Institute of Electrical and Electronics Engineers Inc.},
  title        = {An Experimental Study of Heterostructure Tunnel FET Nanowire Arrays : Digital and Analog Figures of Merit from 300K to 10K},
  url          = {http://dx.doi.org/10.1109/IEDM.2018.8614665},
  volume       = {2018},
  year         = {2019},
}