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A Floating-Point 16 × 16 SVD Accelerator for Beyond-5G Large Intelligent Surfaces

Attari, Mohammad LU ; Sanchez, Jesus Rodriguez LU and Liu, Liang LU orcid (2023) 2023 IEEE 66th International Midwest Symposium on Circuits and Systems, MWSCAS 2023 p.967-971
Abstract

Beyond-5G wireless communication systems will feature advanced, key technologies such as large intelligent surfaces (LISs) composed of a very large number of antenna elements. The concomitant tremendous data rate requirements, due to the communication between these antennas, necessitate careful algorithm-architecture codesign. This paper presents an application-specific integrated circuit (ASIC) accelerator designed for efficient computation of singular value decomposition (SVD) utilized in distributed and scalable massive multiple-input multiple-output (MIMO) systems equipped with LISs. The design supports SVD calculation for 8 × 8 and 16 × 16 matrices and is synthesized using the GF -22nm fully depleted silicon-on-insulator (FD-SOI)... (More)

Beyond-5G wireless communication systems will feature advanced, key technologies such as large intelligent surfaces (LISs) composed of a very large number of antenna elements. The concomitant tremendous data rate requirements, due to the communication between these antennas, necessitate careful algorithm-architecture codesign. This paper presents an application-specific integrated circuit (ASIC) accelerator designed for efficient computation of singular value decomposition (SVD) utilized in distributed and scalable massive multiple-input multiple-output (MIMO) systems equipped with LISs. The design supports SVD calculation for 8 × 8 and 16 × 16 matrices and is synthesized using the GF -22nm fully depleted silicon-on-insulator (FD-SOI) technology with a clock frequency approaching 580 MHz. It takes up an area of 0.33 mm2 and consumes 219 mW of power. The system can pump out results at a cadence of 270/90 kSVDs/s, with a mean squared error (MSE) of 10-3, for 8 × 8 and 16 × 16 matrices, respectively.

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Please use this url to cite or link to this publication:
author
; and
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
accelerator, floating-point, Golub-Kahan, hardware, Jacobi, large intelligent surface, massive MIMO, Singular value decomposition
host publication
2023 IEEE 66th International Midwest Symposium on Circuits and Systems, MWSCAS 2023
pages
5 pages
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
conference name
2023 IEEE 66th International Midwest Symposium on Circuits and Systems, MWSCAS 2023
conference location
Tempe, United States
conference dates
2023-08-06 - 2023-08-09
external identifiers
  • scopus:85185376092
ISBN
9798350302103
DOI
10.1109/MWSCAS57524.2023.10406077
language
English
LU publication?
yes
id
7fde9d1f-8531-4387-b570-5cf1a8684820
date added to LUP
2024-03-18 16:16:44
date last changed
2024-04-01 12:34:20
@inproceedings{7fde9d1f-8531-4387-b570-5cf1a8684820,
  abstract     = {{<p>Beyond-5G wireless communication systems will feature advanced, key technologies such as large intelligent surfaces (LISs) composed of a very large number of antenna elements. The concomitant tremendous data rate requirements, due to the communication between these antennas, necessitate careful algorithm-architecture codesign. This paper presents an application-specific integrated circuit (ASIC) accelerator designed for efficient computation of singular value decomposition (SVD) utilized in distributed and scalable massive multiple-input multiple-output (MIMO) systems equipped with LISs. The design supports SVD calculation for 8 × 8 and 16 × 16 matrices and is synthesized using the GF -22nm fully depleted silicon-on-insulator (FD-SOI) technology with a clock frequency approaching 580 MHz. It takes up an area of 0.33 mm2 and consumes 219 mW of power. The system can pump out results at a cadence of 270/90 kSVDs/s, with a mean squared error (MSE) of 10-3, for 8 × 8 and 16 × 16 matrices, respectively.</p>}},
  author       = {{Attari, Mohammad and Sanchez, Jesus Rodriguez and Liu, Liang}},
  booktitle    = {{2023 IEEE 66th International Midwest Symposium on Circuits and Systems, MWSCAS 2023}},
  isbn         = {{9798350302103}},
  keywords     = {{accelerator; floating-point; Golub-Kahan; hardware; Jacobi; large intelligent surface; massive MIMO; Singular value decomposition}},
  language     = {{eng}},
  pages        = {{967--971}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  title        = {{A Floating-Point 16 × 16 SVD Accelerator for Beyond-5G Large Intelligent Surfaces}},
  url          = {{http://dx.doi.org/10.1109/MWSCAS57524.2023.10406077}},
  doi          = {{10.1109/MWSCAS57524.2023.10406077}},
  year         = {{2023}},
}