Power Constrained Test Scheduling for 3D Stacked Chips: poster
Sengupta, Breeta LU ; Ingelsson, Urban and Larsson, Erik LU
(2010)
1st IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/2340810
- author
- Sengupta, Breeta
LU
; Ingelsson, Urban
and Larsson, Erik
LU
- organization
- publishing date
- 2010
- type
- Contribution to conference
- publication status
- published
- subject
- conference name
- 1st IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits
- conference location
- Austin, United States
- conference dates
- 2010-11-04 - 2010-11-05
- language
- English
- LU publication?
- no
- id
- 844b79c2-f01f-455f-8acc-53b3e9ee2a47 (old id 2340810)
- date added to LUP
- 2016-04-04 13:24:24
- date last changed
- 2020-06-10 15:42:06
@misc{844b79c2-f01f-455f-8acc-53b3e9ee2a47,
author = {{Sengupta, Breeta and Ingelsson, Urban and Larsson, Erik}},
language = {{eng}},
title = {{Power Constrained Test Scheduling for 3D Stacked Chips: poster}},
url = {{https://lup.lub.lu.se/search/files/80474110/4857444.pdf}},
year = {{2010}},
}