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The Harmonized Parabolic Synthesis Methodology for Hardware Efficient Function Generation with Full Error Control

Hertz, Erik LU ; Lai, Jingou; Svensson, Bertil and Nilsson, Peter LU (2017) In Journal of Signal Processing Systems2008-01-01+01:00
Abstract

The Harmonized Parabolic Synthesis methodology is a further development of the Parabolic Synthesis methodology for approximation of unary functions such as trigonometric functions, logarithms and the square root with moderate accuracy for ASIC implementation. These functions are extensively used in computer graphics, communication systems and many other application areas. For these high-speed applications, software solutions are not sufficient, and a hardware implementation is therefore needed. The Harmonized Parabolic Synthesis methodology has two outstanding advantages: it is parallel, thus reducing the execution time, and it is based on low complexity operations, thus being simple to implement in hardware. A difference compared to... (More)

The Harmonized Parabolic Synthesis methodology is a further development of the Parabolic Synthesis methodology for approximation of unary functions such as trigonometric functions, logarithms and the square root with moderate accuracy for ASIC implementation. These functions are extensively used in computer graphics, communication systems and many other application areas. For these high-speed applications, software solutions are not sufficient, and a hardware implementation is therefore needed. The Harmonized Parabolic Synthesis methodology has two outstanding advantages: it is parallel, thus reducing the execution time, and it is based on low complexity operations, thus being simple to implement in hardware. A difference compared to other approximation methodologies is that it is a multiplicative, and not additive, methodology. Compared to the Parabolic Synthesis methodologies it is possible to significantly enhance the performance in terms of reducing chip area, computation delay and power consumption. Furthermore, it increases the possibility to tailor the characteristics of the error, improving conditions for subsequent calculations. To evaluate the methodology, the fractional part of the logarithm is implemented and its performance is compared to the Parabolic Synthesis methodology. The comparison is made with 15-bit resolution. The design implemented using the proposed methodology performs 3× better than the Parabolic Synthesis implementation in terms of throughput, while consuming 90% less energy. The chip area is 70% smaller than for the Parabolic Synthesis methodology. In summary, the new technology further increases the advantages of Parabolic Synthesis.

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author
organization
publishing date
type
Contribution to journal
publication status
epub
subject
keywords
Approximation, Arithmetic computation, Elementary functions, Look-up table, Parabolic synthesis, Second-degree interpolation, Unary functions, VLSI
in
Journal of Signal Processing Systems2008-01-01+01:00
pages
15 pages
publisher
Springer
external identifiers
  • scopus:85032329367
ISSN
1939-8018
DOI
10.1007/s11265-017-1300-4
language
English
LU publication?
yes
id
8f527c88-718c-4a3f-a161-154757192a7f
date added to LUP
2017-11-07 13:25:56
date last changed
2017-11-07 13:25:56
@article{8f527c88-718c-4a3f-a161-154757192a7f,
  abstract     = {<p>The Harmonized Parabolic Synthesis methodology is a further development of the Parabolic Synthesis methodology for approximation of unary functions such as trigonometric functions, logarithms and the square root with moderate accuracy for ASIC implementation. These functions are extensively used in computer graphics, communication systems and many other application areas. For these high-speed applications, software solutions are not sufficient, and a hardware implementation is therefore needed. The Harmonized Parabolic Synthesis methodology has two outstanding advantages: it is parallel, thus reducing the execution time, and it is based on low complexity operations, thus being simple to implement in hardware. A difference compared to other approximation methodologies is that it is a multiplicative, and not additive, methodology. Compared to the Parabolic Synthesis methodologies it is possible to significantly enhance the performance in terms of reducing chip area, computation delay and power consumption. Furthermore, it increases the possibility to tailor the characteristics of the error, improving conditions for subsequent calculations. To evaluate the methodology, the fractional part of the logarithm is implemented and its performance is compared to the Parabolic Synthesis methodology. The comparison is made with 15-bit resolution. The design implemented using the proposed methodology performs 3× better than the Parabolic Synthesis implementation in terms of throughput, while consuming 90% less energy. The chip area is 70% smaller than for the Parabolic Synthesis methodology. In summary, the new technology further increases the advantages of Parabolic Synthesis.</p>},
  author       = {Hertz, Erik and Lai, Jingou and Svensson, Bertil and Nilsson, Peter},
  issn         = {1939-8018},
  keyword      = {Approximation,Arithmetic computation,Elementary functions,Look-up table,Parabolic synthesis,Second-degree interpolation,Unary functions,VLSI},
  language     = {eng},
  month        = {10},
  pages        = {15},
  publisher    = {Springer},
  series       = {Journal of Signal Processing Systems2008-01-01+01:00},
  title        = {The Harmonized Parabolic Synthesis Methodology for Hardware Efficient Function Generation with Full Error Control},
  url          = {http://dx.doi.org/10.1007/s11265-017-1300-4},
  year         = {2017},
}