A digitally controlled shunt capacitor CMOS delay line
(1999) In Analog Integrated Circuits and Signal Processing 18(1). p.89-96- Abstract
- Delay-controlled CMOS delay lines have been proved useful in a number of applications, notably the digitization of short time intervals. This paper introduces a new kind of CMOS delay line, in which the delay element is an array of capacitors controlled by a digital signal vector. This choice allows for a robust implementation of the circuitry controlling the delay generation, while the maximum speed attainable by the line is high compared to the maximum speed achieved by other delay line architectures. The delay line presented here was designed to produce an accurately tunable 16 x 0.5 ns delay under large temperature, supply voltage, and technological process quality variations.
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/1051606
- author
- Andreani, Pietro LU ; Bigongiari, Franco ; Roncella, Roberto ; Saletti, Roberto and Terreni, Pierangelo
- organization
- publishing date
- 1999
- type
- Contribution to journal
- publication status
- published
- subject
- in
- Analog Integrated Circuits and Signal Processing
- volume
- 18
- issue
- 1
- pages
- 89 - 96
- publisher
- Springer
- external identifiers
-
- scopus:0032625762
- ISSN
- 0925-1030
- DOI
- 10.1023/A:1008359721539
- language
- English
- LU publication?
- yes
- additional info
- The information about affiliations in this record was updated in December 2015. The record was previously connected to the following departments: Department of Electroscience (011041000)
- id
- 906996c0-f862-4f9a-96ed-499bdc149d17 (old id 1051606)
- date added to LUP
- 2016-04-04 09:33:03
- date last changed
- 2022-01-29 18:21:49
@article{906996c0-f862-4f9a-96ed-499bdc149d17, abstract = {{Delay-controlled CMOS delay lines have been proved useful in a number of applications, notably the digitization of short time intervals. This paper introduces a new kind of CMOS delay line, in which the delay element is an array of capacitors controlled by a digital signal vector. This choice allows for a robust implementation of the circuitry controlling the delay generation, while the maximum speed attainable by the line is high compared to the maximum speed achieved by other delay line architectures. The delay line presented here was designed to produce an accurately tunable 16 x 0.5 ns delay under large temperature, supply voltage, and technological process quality variations.}}, author = {{Andreani, Pietro and Bigongiari, Franco and Roncella, Roberto and Saletti, Roberto and Terreni, Pierangelo}}, issn = {{0925-1030}}, language = {{eng}}, number = {{1}}, pages = {{89--96}}, publisher = {{Springer}}, series = {{Analog Integrated Circuits and Signal Processing}}, title = {{A digitally controlled shunt capacitor CMOS delay line}}, url = {{http://dx.doi.org/10.1023/A:1008359721539}}, doi = {{10.1023/A:1008359721539}}, volume = {{18}}, year = {{1999}}, }