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Modelling and optimization of III/V transistors with matrices of nanowires

Larsen, Christian; Ärlelid, Mats LU ; Lind, Erik LU and Wernersson, Lars-Erik LU (2010) In Solid-State Electronics 54(12). p.1505-1510
Abstract
The magnitude and Impact of the parasitic capacitances in a vertical InAs nanowire transistor consisting of a matrix of nanowires is evaluated A simple transistor model is fitted to experimental I-V characteristics and the influence of the parasitic components on the transistor performance for different structures is investigated Simulations of the S parameters indicate an intrinsic f(T) of about 690 GHz for 50 nm L-G We show that f(T) reaches 56% of the intrinsic value in an optimized transistor structure with closely spaced nanowires and that a high wire density is more efficient to reduce the parasitics than to pattern the electrodes Finally the analytical model is used to demonstrate the operation and to simulate the performance of... (More)
The magnitude and Impact of the parasitic capacitances in a vertical InAs nanowire transistor consisting of a matrix of nanowires is evaluated A simple transistor model is fitted to experimental I-V characteristics and the influence of the parasitic components on the transistor performance for different structures is investigated Simulations of the S parameters indicate an intrinsic f(T) of about 690 GHz for 50 nm L-G We show that f(T) reaches 56% of the intrinsic value in an optimized transistor structure with closely spaced nanowires and that a high wire density is more efficient to reduce the parasitics than to pattern the electrodes Finally the analytical model is used to demonstrate the operation and to simulate the performance of ring-oscillators (C) 2010 Elsevier Ltd All rights reserved (Less)
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Contribution to journal
publication status
published
subject
keywords
Wrap gate, InAs, Ring oscillator, Nanowire, Field Effect Transistor
in
Solid-State Electronics
volume
54
issue
12
pages
1505 - 1510
publisher
Elsevier
external identifiers
  • wos:000283978000004
  • scopus:77957317458
ISSN
0038-1101
DOI
10.1016/j.sse.2010.06.017
language
English
LU publication?
yes
id
a419eac5-f614-4d22-a782-447ecdf2d4cb (old id 1752742)
date added to LUP
2010-12-30 07:38:00
date last changed
2018-01-07 03:32:46
@article{a419eac5-f614-4d22-a782-447ecdf2d4cb,
  abstract     = {The magnitude and Impact of the parasitic capacitances in a vertical InAs nanowire transistor consisting of a matrix of nanowires is evaluated A simple transistor model is fitted to experimental I-V characteristics and the influence of the parasitic components on the transistor performance for different structures is investigated Simulations of the S parameters indicate an intrinsic f(T) of about 690 GHz for 50 nm L-G We show that f(T) reaches 56% of the intrinsic value in an optimized transistor structure with closely spaced nanowires and that a high wire density is more efficient to reduce the parasitics than to pattern the electrodes Finally the analytical model is used to demonstrate the operation and to simulate the performance of ring-oscillators (C) 2010 Elsevier Ltd All rights reserved},
  author       = {Larsen, Christian and Ärlelid, Mats and Lind, Erik and Wernersson, Lars-Erik},
  issn         = {0038-1101},
  keyword      = {Wrap gate,InAs,Ring oscillator,Nanowire,Field Effect Transistor},
  language     = {eng},
  number       = {12},
  pages        = {1505--1510},
  publisher    = {Elsevier},
  series       = {Solid-State Electronics},
  title        = {Modelling and optimization of III/V transistors with matrices of nanowires},
  url          = {http://dx.doi.org/10.1016/j.sse.2010.06.017},
  volume       = {54},
  year         = {2010},
}