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2023
Mark High-k/InGaAs interface defects at cryogenic temperature
Cherkaoui, K. ^LU ; La Torraca, P. ; Lin, J. ; Maraviglia, N. ; Andersen, A. ^LU ; Wernersson, L. E. ^LU ; Padovani, A. ; Larcher, L. and Hurley, P. K. (2023) In Solid-State Electronics 207.
- Contribution to journal › Article
2020
Mark Effects of traps in the gate stack on the small-signal RF response of III-V nanowire MOSFETs
Hellenbrand, Markus ^LU ; Lind, Erik ^LU ; Kilpi, Olli-Pekka ^LU and Wernersson, Lars-Erik ^LU (2020) In Solid-State Electronics 171.
- Contribution to journal › Article
2016
Mark Ballistic modeling of InAs nanowire transistors
Jansson, Kristofer ^LU ; Lind, Erik ^LU and Wernersson, Lars-Erik ^LU (2016) In Solid-State Electronics 115. p.47-53
- Contribution to journal › Article
2010
Mark Modelling and optimization of III/V transistors with matrices of nanowires
Larsen, Christian ; Ärlelid, Mats ^LU ; Lind, Erik ^LU and Wernersson, Lars-Erik ^LU (2010) In Solid-State Electronics 54(12). p.1505-1510
- Contribution to journal › Article
2009
Mark Gated tunnel diode in oscillator applications with high frequency tuning
Wernersson, Lars-Erik ^LU ; Ärlelid, Mats ^LU ; Egard, Mikael ^LU and Lind, Erik ^LU (2009) In Solid-State Electronics 53(3). p.292-296
- Contribution to journal › Article
2002
Mark Reduction of the Schottky barrier height on silicon carbide using Au nano-particles
Lee, SK ; Zetterling, CM ; Ostling, M ; Åberg, I ; Magnusson, Martin ^LU ; Deppert, Knut ^LU ; Wernersson, Lars-Erik ^LU ; Samuelson, Lars ^LU and Litwin, A (2002) In Solid-State Electronics 46(9). p.1433-1440
- Contribution to journal › Article

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