Co-optimization of security and accessibility to on-chip instruments
Larsson, Erik LU
(2023)
24th IEEE Latin-American Test Symposium, LATS 2023
- Abstract
- The semiconductor technology development con- stantly enables integrated circuits (ICs) with more, faster and smaller transistors. While there are many advantages, there are also many and new challenges, for example tighter margins, wear- outs and process variations. To address these challenges, the traditional approach with external test instruments used at man- ufacturing test must be complemented with on-chip instruments to provide possibilities to test for defects that manifest themselves during the operational lifetime. These on-chip instruments provide, on one hand, better controllability and observability, which is helpful for testing purposes. On the other hand, the increased possibility to control and observable the IC’s internals... (More)
- The semiconductor technology development con- stantly enables integrated circuits (ICs) with more, faster and smaller transistors. While there are many advantages, there are also many and new challenges, for example tighter margins, wear- outs and process variations. To address these challenges, the traditional approach with external test instruments used at man- ufacturing test must be complemented with on-chip instruments to provide possibilities to test for defects that manifest themselves during the operational lifetime. These on-chip instruments provide, on one hand, better controllability and observability, which is helpful for testing purposes. On the other hand, the increased possibility to control and observable the IC’s internals can be a security risk. We discuss how to provide access and how to co- optimize security and accessibility for these on-chip instruments. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/a6d4fcbe-6073-4e79-ab67-5ce49cc10c7a
- author
- Larsson, Erik
LU
- organization
- publishing date
- 2023
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- host publication
- 2023 IEEE 24th Latin American Test Symposium (LATS)
- pages
- 2 pages
- conference name
- 24th IEEE Latin-American Test Symposium, LATS 2023
- conference location
- Veracruz, Mexico
- conference dates
- 2023-03-21 - 2023-03-24
- external identifiers
-
- scopus:85164688116
- ISBN
- 979-835032597-3
- DOI
- 10.1109/LATS58125.2023.10154500
- language
- English
- LU publication?
- yes
- id
- a6d4fcbe-6073-4e79-ab67-5ce49cc10c7a
- date added to LUP
- 2023-06-19 10:01:52
- date last changed
- 2023-09-25 14:31:35
@inproceedings{a6d4fcbe-6073-4e79-ab67-5ce49cc10c7a,
abstract = {{The semiconductor technology development con- stantly enables integrated circuits (ICs) with more, faster and smaller transistors. While there are many advantages, there are also many and new challenges, for example tighter margins, wear- outs and process variations. To address these challenges, the traditional approach with external test instruments used at man- ufacturing test must be complemented with on-chip instruments to provide possibilities to test for defects that manifest themselves during the operational lifetime. These on-chip instruments provide, on one hand, better controllability and observability, which is helpful for testing purposes. On the other hand, the increased possibility to control and observable the IC’s internals can be a security risk. We discuss how to provide access and how to co- optimize security and accessibility for these on-chip instruments.}},
author = {{Larsson, Erik}},
booktitle = {{2023 IEEE 24th Latin American Test Symposium (LATS)}},
isbn = {{979-835032597-3}},
language = {{eng}},
title = {{Co-optimization of security and accessibility to on-chip instruments}},
url = {{https://lup.lub.lu.se/search/files/159462128/main.pdf}},
doi = {{10.1109/LATS58125.2023.10154500}},
year = {{2023}},
}