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A Technique to Increase the Linearity of the Bootstrapped Switch

Karrari, Hamid LU ; Andreani, Pietro LU and Tan, Siyu LU (2023) 2023 IEEE 66th International Midwest Symposium on Circuits and Systems, MWSCAS 2023 p.1001-1004
Abstract

We present a detailed investigation into a source of distortion that affects the classic bootstrapped switch. Our analysis reveals that the transition phase between track mode and hold mode is a critical factor in causing the distortion. To address this issue, we propose a novel technique that effectively mitigates the problem. Our results, based on simulations conducted using a 22-nm FDSOI CMOS process, show an improvement of at least 4 dB in the signal-to-distortion ratio, with only a minor reduction in signal bandwidth. Importantly, the increase in SDR is achieved with a minimum cost in terms of power consumption and area occupation.

Please use this url to cite or link to this publication:
author
; and
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
analog-to-digital converter (ADC), bootstrapped switch, linearity, sample-and-hold (S/H)
host publication
2023 IEEE 66th International Midwest Symposium on Circuits and Systems, MWSCAS 2023
pages
4 pages
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
conference name
2023 IEEE 66th International Midwest Symposium on Circuits and Systems, MWSCAS 2023
conference location
Tempe, United States
conference dates
2023-08-06 - 2023-08-09
external identifiers
  • scopus:85185373473
ISBN
9798350302103
DOI
10.1109/MWSCAS57524.2023.10405965
language
English
LU publication?
yes
id
be3dc502-3675-45a0-acf5-c0087f043be8
date added to LUP
2024-03-18 15:11:55
date last changed
2025-10-14 11:08:35
@inproceedings{be3dc502-3675-45a0-acf5-c0087f043be8,
  abstract     = {{<p>We present a detailed investigation into a source of distortion that affects the classic bootstrapped switch. Our analysis reveals that the transition phase between track mode and hold mode is a critical factor in causing the distortion. To address this issue, we propose a novel technique that effectively mitigates the problem. Our results, based on simulations conducted using a 22-nm FDSOI CMOS process, show an improvement of at least 4 dB in the signal-to-distortion ratio, with only a minor reduction in signal bandwidth. Importantly, the increase in SDR is achieved with a minimum cost in terms of power consumption and area occupation.</p>}},
  author       = {{Karrari, Hamid and Andreani, Pietro and Tan, Siyu}},
  booktitle    = {{2023 IEEE 66th International Midwest Symposium on Circuits and Systems, MWSCAS 2023}},
  isbn         = {{9798350302103}},
  keywords     = {{analog-to-digital converter (ADC); bootstrapped switch; linearity; sample-and-hold (S/H)}},
  language     = {{eng}},
  pages        = {{1001--1004}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  title        = {{A Technique to Increase the Linearity of the Bootstrapped Switch}},
  url          = {{http://dx.doi.org/10.1109/MWSCAS57524.2023.10405965}},
  doi          = {{10.1109/MWSCAS57524.2023.10405965}},
  year         = {{2023}},
}