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An Application Specific Vector Processor for Efficient Massive MIMO Processing

Attari, Mohammad LU ; Ferreira, Lucas LU ; Liu, Liang LU orcid and Malkowsky, Steffen LU (2022) In IEEE Transactions on Circuits and Systems I: Regular Papers p.1-12
Abstract

This paper presents an implementation for a baseband massive multiple-input multiple-output (MIMO) application-specific instruction set processor (ASIP). The ASIP is geared with vector processing capabilities in the form of single instruction multiple data (SIMD), and furthermore exploits instruction level parallelism by employing a very large instruction word (VLIW) architecture. Additionally, a systolic array is built into the pipeline which is tuned to speed up matrix calculations. A parallel memory subsystem and stand-alone accelerators are integrated into the ASIP architecture in order to meet the processing requirement. The processor is synthesized in 22FD-SOI technology running at a clock frequency of 800 . The system achieves a... (More)

This paper presents an implementation for a baseband massive multiple-input multiple-output (MIMO) application-specific instruction set processor (ASIP). The ASIP is geared with vector processing capabilities in the form of single instruction multiple data (SIMD), and furthermore exploits instruction level parallelism by employing a very large instruction word (VLIW) architecture. Additionally, a systolic array is built into the pipeline which is tuned to speed up matrix calculations. A parallel memory subsystem and stand-alone accelerators are integrated into the ASIP architecture in order to meet the processing requirement. The processor is synthesized in 22FD-SOI technology running at a clock frequency of 800 . The system achieves a maximum detection throughput of 0.75 Gb/s/mm<inline-formula> <tex-math notation="LaTeX">$^2$</tex-math> </inline-formula> for a <inline-formula> <tex-math notation="LaTeX">$128\times 8$</tex-math> </inline-formula> massive MIMO system.

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Please use this url to cite or link to this publication:
author
; ; and
organization
publishing date
type
Contribution to journal
publication status
published
subject
keywords
5G, accelerator architecture, ASIP, Baseband, baseband processor, communications processor, Complexity theory, Computer architecture, computer architecture, Massive MIMO, massive MIMO, Mathematical models, Matrix decomposition, matrix processor, parallel memory, Precoding, programmable processor, SIMD, systolic arrays, vector processor, VLIW
in
IEEE Transactions on Circuits and Systems I: Regular Papers
pages
12 pages
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
external identifiers
  • scopus:85133752581
ISSN
1549-8328
DOI
10.1109/TCSI.2022.3182483
language
English
LU publication?
yes
id
cf3b4f54-3d7f-452b-bb06-69ba520aee3f
date added to LUP
2022-09-06 13:55:54
date last changed
2024-03-21 13:30:30
@article{cf3b4f54-3d7f-452b-bb06-69ba520aee3f,
  abstract     = {{<p>This paper presents an implementation for a baseband massive multiple-input multiple-output (MIMO) application-specific instruction set processor (ASIP). The ASIP is geared with vector processing capabilities in the form of single instruction multiple data (SIMD), and furthermore exploits instruction level parallelism by employing a very large instruction word (VLIW) architecture. Additionally, a systolic array is built into the pipeline which is tuned to speed up matrix calculations. A parallel memory subsystem and stand-alone accelerators are integrated into the ASIP architecture in order to meet the processing requirement. The processor is synthesized in 22FD-SOI technology running at a clock frequency of 800 . The system achieves a maximum detection throughput of 0.75 Gb/s/mm&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$^2$&lt;/tex-math&gt; &lt;/inline-formula&gt; for a &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$128\times 8$&lt;/tex-math&gt; &lt;/inline-formula&gt; massive MIMO system.</p>}},
  author       = {{Attari, Mohammad and Ferreira, Lucas and Liu, Liang and Malkowsky, Steffen}},
  issn         = {{1549-8328}},
  keywords     = {{5G; accelerator architecture; ASIP; Baseband; baseband processor; communications processor; Complexity theory; Computer architecture; computer architecture; Massive MIMO; massive MIMO; Mathematical models; Matrix decomposition; matrix processor; parallel memory; Precoding; programmable processor; SIMD; systolic arrays; vector processor; VLIW}},
  language     = {{eng}},
  pages        = {{1--12}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  series       = {{IEEE Transactions on Circuits and Systems I: Regular Papers}},
  title        = {{An Application Specific Vector Processor for Efficient Massive MIMO Processing}},
  url          = {{http://dx.doi.org/10.1109/TCSI.2022.3182483}},
  doi          = {{10.1109/TCSI.2022.3182483}},
  year         = {{2022}},
}