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Impact of Layout on the RF Performance of Vertical In–Ga–As Nanowire MOSFETs

Sandberg, Marcus E. LU orcid ; Löfstrand, Anette LU ; Svensson, Johannes LU and Fhager, Lars LU orcid (2025) In IEEE Microwave and Wireless Technology Letters
Abstract

High-speed vertical In–Ga–As nanowire MOS field-effect transistor (MOSFET) measurements were analyzed through parametric layout models. Measurements from small and large transistors were used to fit dependencies on the number of gate fingers and the number of wires per finger. Extrapolations via intrinsic and parasitic elements reveal the optimal layout for peak frequency performance. To achieve a scalable technology platform, the process flow was here also reworked and simplified. In conjunction with refined feeder patterning, addition of a drain spacer, and reduced gate lengths previously demonstrated, the results indicate a viable path for strongly improved frequency performance in the technology.

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author
; ; and
organization
publishing date
type
Contribution to journal
publication status
epub
subject
keywords
III-V compound semiconductor, modeling, MOS field-effect transistors (MOSFETs), radio frequency (RF), vertical nanowire
in
IEEE Microwave and Wireless Technology Letters
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
external identifiers
  • scopus:105006911317
ISSN
2771-957X
DOI
10.1109/LMWT.2025.3571131
language
English
LU publication?
yes
additional info
Publisher Copyright: © 2023 IEEE.
id
e7a68795-5d80-4d2a-b2d0-07ff7549ab1a
date added to LUP
2025-08-15 12:57:08
date last changed
2025-08-16 03:29:36
@article{e7a68795-5d80-4d2a-b2d0-07ff7549ab1a,
  abstract     = {{<p>High-speed vertical In–Ga–As nanowire MOS field-effect transistor (MOSFET) measurements were analyzed through parametric layout models. Measurements from small and large transistors were used to fit dependencies on the number of gate fingers and the number of wires per finger. Extrapolations via intrinsic and parasitic elements reveal the optimal layout for peak frequency performance. To achieve a scalable technology platform, the process flow was here also reworked and simplified. In conjunction with refined feeder patterning, addition of a drain spacer, and reduced gate lengths previously demonstrated, the results indicate a viable path for strongly improved frequency performance in the technology.</p>}},
  author       = {{Sandberg, Marcus E. and Löfstrand, Anette and Svensson, Johannes and Fhager, Lars}},
  issn         = {{2771-957X}},
  keywords     = {{III-V compound semiconductor; modeling; MOS field-effect transistors (MOSFETs); radio frequency (RF); vertical nanowire}},
  language     = {{eng}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  series       = {{IEEE Microwave and Wireless Technology Letters}},
  title        = {{Impact of Layout on the RF Performance of Vertical In–Ga–As Nanowire MOSFETs}},
  url          = {{http://dx.doi.org/10.1109/LMWT.2025.3571131}},
  doi          = {{10.1109/LMWT.2025.3571131}},
  year         = {{2025}},
}