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A 1.4 GS/s TI Pipelined-SAR analog-to-digital converter in 22-nm FDSOI CMOS

Karrari, Hamid LU ; Andreani, Pietro LU and Tan, Siyu LU (2023) 9th IEEE Nordic Circuits and Systems Conference, NorCAS 2023 In 2023 IEEE Nordic Circuits and Systems Conference, NorCAS 2023 - Proceedings
Abstract

This paper presents a 4-channel time-interleaved (TI) analog-to-digital converter (ADC), where each channel is comprised of a two-stage pipelined asynchronous successive-approximation (ASAR) sub-ADC. The ADC employs two samplers to alleviate the problem of timing skew on the sub-sampler when distributing the clock to the TI channels. To further increase the speed of the ADC, the reset switch in the capacitive digital-to-analog converter of each sub-ADC is also boot-strapped. The ADC is implemented in a 22-nm CMOS FDSOI technology. With a sampling rate of 1.4 GS/s, measurements show that the ADC achieves an SNDR of 50 dB with a low-frequency input. The SNDR drops by only 1.5 dB at Nyquist. Powered by a 0.8 V supply, the total power... (More)

This paper presents a 4-channel time-interleaved (TI) analog-to-digital converter (ADC), where each channel is comprised of a two-stage pipelined asynchronous successive-approximation (ASAR) sub-ADC. The ADC employs two samplers to alleviate the problem of timing skew on the sub-sampler when distributing the clock to the TI channels. To further increase the speed of the ADC, the reset switch in the capacitive digital-to-analog converter of each sub-ADC is also boot-strapped. The ADC is implemented in a 22-nm CMOS FDSOI technology. With a sampling rate of 1.4 GS/s, measurements show that the ADC achieves an SNDR of 50 dB with a low-frequency input. The SNDR drops by only 1.5 dB at Nyquist. Powered by a 0.8 V supply, the total power consumption of the ADC is 37.5 mW, while the ADC core consumes 19.3 mW.

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Please use this url to cite or link to this publication:
author
; and
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
Analog-to-digital converter (ADC), dynamic amplifier (DA), Pipeline, Successive approximation (SAR), Time-interleaved (TI)
host publication
2023 IEEE Nordic Circuits and Systems Conference, NorCAS 2023 - Proceedings
series title
2023 IEEE Nordic Circuits and Systems Conference, NorCAS 2023 - Proceedings
editor
Nurmi, Jari ; Ellervee, Peeter ; Koch, Peter ; Moradi, Farshad and Shen, Ming
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
conference name
9th IEEE Nordic Circuits and Systems Conference, NorCAS 2023
conference location
Aalborg, Denmark
conference dates
2023-10-31 - 2023-11-01
external identifiers
  • scopus:85179504318
ISBN
9798350337570
DOI
10.1109/NorCAS58970.2023.10305443
language
English
LU publication?
yes
id
f0243944-bb6d-44f5-acf0-75bd5d63913e
date added to LUP
2024-01-11 11:45:24
date last changed
2024-01-11 11:46:29
@inproceedings{f0243944-bb6d-44f5-acf0-75bd5d63913e,
  abstract     = {{<p>This paper presents a 4-channel time-interleaved (TI) analog-to-digital converter (ADC), where each channel is comprised of a two-stage pipelined asynchronous successive-approximation (ASAR) sub-ADC. The ADC employs two samplers to alleviate the problem of timing skew on the sub-sampler when distributing the clock to the TI channels. To further increase the speed of the ADC, the reset switch in the capacitive digital-to-analog converter of each sub-ADC is also boot-strapped. The ADC is implemented in a 22-nm CMOS FDSOI technology. With a sampling rate of 1.4 GS/s, measurements show that the ADC achieves an SNDR of 50 dB with a low-frequency input. The SNDR drops by only 1.5 dB at Nyquist. Powered by a 0.8 V supply, the total power consumption of the ADC is 37.5 mW, while the ADC core consumes 19.3 mW.</p>}},
  author       = {{Karrari, Hamid and Andreani, Pietro and Tan, Siyu}},
  booktitle    = {{2023 IEEE Nordic Circuits and Systems Conference, NorCAS 2023 - Proceedings}},
  editor       = {{Nurmi, Jari and Ellervee, Peeter and Koch, Peter and Moradi, Farshad and Shen, Ming}},
  isbn         = {{9798350337570}},
  keywords     = {{Analog-to-digital converter (ADC); dynamic amplifier (DA); Pipeline; Successive approximation (SAR); Time-interleaved (TI)}},
  language     = {{eng}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  series       = {{2023 IEEE Nordic Circuits and Systems Conference, NorCAS 2023 - Proceedings}},
  title        = {{A 1.4 GS/s TI Pipelined-SAR analog-to-digital converter in 22-nm FDSOI CMOS}},
  url          = {{http://dx.doi.org/10.1109/NorCAS58970.2023.10305443}},
  doi          = {{10.1109/NorCAS58970.2023.10305443}},
  year         = {{2023}},
}