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- 2009
-
Mark
Scan Cell Reordering to Minimize Peak Power during Scan Testing of SoC
(
- Contribution to conference › Paper, not in proceeding
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Mark
On Scan Chain Diagnosis for Intermittent Faults
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Capture Power Reduction for Modular System-on-Chip Test
2009) IEEE/VSI VLSI Design and Test Symposium (VDAT)(
- Contribution to conference › Paper, not in proceeding
-
Mark
Generation of Minimal Leakage Input Vectors with Constrained NBTI Degradation
(
- Contribution to conference › Paper, not in proceeding
- 2008
-
Mark
An Architecture for Integrated Test Data Compression and Abort-on-Fail Testing in a Multi-Site Environment
(
- Contribution to journal › Article
-
Mark
An Integrated System-on-Chip Test Framework
2008) p.439-454(
- Chapter in Book/Report/Conference proceeding › Book chapter
-
Mark
A reconfigurable power conscious core wrapper and its application to system-on-chip test scheduling
(
- Contribution to journal › Article
-
Mark
Test Response Compression for Diagnosis in Volume Production
2008) DAC08 Workshop on Diagnostic Services in Network-on-Chips DSNOC(
- Contribution to conference › Paper, not in proceeding
-
Mark
On Reduction of Capture Power for Modular System-on-Chip Test
2008) IEEE Workshop on RTL and High Level Testing WRTLT08(
- Contribution to conference › Paper, not in proceeding
-
Mark
Core-Level Expansion of Compressed Test Patterns
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding