111 – 120 of 179
- show: 10
- |
- sort: year (new to old)
Close
Embed this list
<iframe src=""
width=""
height=""
allowtransparency="true"
frameborder="0">
</iframe>
- 2009
-
Mark
Capture Power Reduction for Modular System-on-Chip Test
Tudu, Jaynarayan T. ; Larsson, Erik LU
; Singh, Virendra
and Singh, Adit
(2009)
IEEE/VSI VLSI Design and Test Symposium (VDAT)
- Contribution to conference › Paper, not in proceeding
-
Mark
Fault-Tolerant Average Execution Time Optimization for System-On-Chips
Väyrynen, Mikael ; Singh, Virendra and Larsson, Erik LU
(2009)
Frontiers of High Performance Embedded Computing
- Contribution to conference › Paper, not in proceeding
-
Mark
Scan Cell Reordering to Minimize Peak Power during Scan Testing of SoC
Tudu, Jaynarayan T. ; Larsson, Erik LU
; Singh, Virendra
and Fujiwara, Hideo
(2009)
10th IEEE Workshop on RTL and High Level Testing (WRTLT'09)
p.43-48
- Contribution to conference › Paper, not in proceeding
-
Mark
An Even-Odd DFD Technique for Scan Chain Diagnosis
Rajesh, Venkat ; Larsson, Erik LU
; Gaur, Manoj S.
and Singh, Virendra
(2009)
Workshop on RTL and High Level Testing (WRTLT)
- Contribution to conference › Paper, not in proceeding
- 2008
-
Mark
Core-Level Expansion of Compressed Test Patterns
Larsson, Anders ; Zhang, Xin ; Larsson, Erik LU
and Chakrabarty, Krishnendu
(2008)
17th Asian Test Symposium ATS
p.277-277
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Test Response Compression for Diagnosis in Volume Production
Söderman, Michael and Larsson, Erik LU
(2008)
DAC08 Workshop on Diagnostic Services in Network-on-Chips DSNOC
- Contribution to conference › Paper, not in proceeding
-
Mark
Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns
Larsson, Anders ; Larsson, Erik LU
; Chakrabarty, Krishnendu
; Eles, Petru Ion
and Peng, Zebo
(2008)
Design, Automation, and Test in Europe DATE 2008
p.188-193
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
An Integrated System-on-Chip Test Framework
- Chapter in Book/Report/Conference proceeding › Book chapter
-
Mark
Cycle-Accurate Test Power Modeling and its Application to SoC Test Architecture Design and Scheduling
Samii, Soheil ; Selkälä, Mikko ; Larsson, Erik LU
; Chakrabarty, Krishnendu
and Peng, Zebo
(2008)
In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
27(5).
p.973-977
- Contribution to journal › Article
-
Mark
An Architecture for Integrated Test Data Compression and Abort-on-Fail Testing in a Multi-Site Environment
- Contribution to journal › Article