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- 2009
-
Mark
On Minimization of Peak Power for Scan Circuit during Test
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Fault-tolerant average execution time optimization for general-purpose multi-processor system-on-chips
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Fault-Tolerant Average Execution Time Optimization for System-On-Chips
(2009) Frontiers of High Performance Embedded Computing
- Contribution to conference › Paper, not in proceeding
- 2008
-
Mark
Cycle-Accurate Test Power Modeling and its Application to SoC Test Architecture Design and Scheduling
(2008) In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27(5). p.973-977
- Contribution to journal › Article
-
Mark
An Architecture for Integrated Test Data Compression and Abort-on-Fail Testing in a Multi-Site Environment
- Contribution to journal › Article
-
Mark
A reconfigurable power conscious core wrapper and its application to system-on-chip test scheduling
- Contribution to journal › Article
-
Mark
On Reduction of Capture Power for Modular System-on-Chip Test
(2008) IEEE Workshop on RTL and High Level Testing WRTLT08
- Contribution to conference › Paper, not in proceeding
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Mark
Test Response Compression for Diagnosis in Volume Production
(2008) DAC08 Workshop on Diagnostic Services in Network-on-Chips DSNOC
- Contribution to conference › Paper, not in proceeding
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Mark
Core-Level Expansion of Compressed Test Patterns
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
