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- 2011
-
Mark
Test Scheduling for 3D Stacked ICs under Power Constraints
(2011) 2nd IEEE International Workshop on Reliability Aware System Design and Test (RASDAT)
- Contribution to conference › Paper, not in proceeding
-
Mark
Study on the Level of Confidence for Roll-back Recovery with Checkpointing
(2011) 1st Intl. Workshop on Dependability Issues in Deep-submicron Technologies (DDT 2011)
- Contribution to conference › Paper, not in proceeding
-
Mark
Design Automation for IEEE P1687
(2011) Design, Automation and Test in Europe (DATE 2011),
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Measurement Point Selection for In-Operation Wear-Out Monitoring
(2011) 14th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS11)
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
SoC-Level Fault Management based on P1687 IJTAG
(2011)
- Other contribution › Miscellaneous
-
Mark
Test Planning for 3D Stacked ICs with Through-Silicon Vias
(2011) Second IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits
- Contribution to conference › Paper, not in proceeding
-
Mark
A Study of Instrument Reuse and Retargeting in P1687
(2011) IEEE Twelfth Workshop on RTL and High Level Testing (WRTLT 2011)
- Contribution to conference › Paper, not in proceeding
-
Mark
Scheduling Tests for 3D Stacked Chips under Power Constraints
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Level of Confidence Evaluation and Its Usage for Roll-back Recovery with Checkpointing Optimization
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Test Cost Modeling for 3D Stacked Chips with Through-Silicon Vias
(2011) Swedish System-on-Chip Conference, SSoCC 2011
- Contribution to conference › Paper, not in proceeding
