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- 2012
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Mark
Test Planning for Core-based 3D Stacked ICs under Power Constraints
2012) IEEE International Workshop on Realiability Aware System Design and Test (RASDAT 2012)(
- Contribution to conference › Paper, not in proceeding
-
Mark
The MCNP Monte Carlo Program
2012) p.153-172(
- Chapter in Book/Report/Conference proceeding › Book chapter
- 2011
-
Mark
Test Scheduling in an IEEE P1687 Environment with Resource and Power Constraints
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Adaptive Execution Assistance for Multiplexed Fault-Tolerant Chip Multiprocessors
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
European Test Symposium (ETS) 2011
(
- Contribution to specialist publication or newspaper › Specialist publication article
-
Mark
Level of Confidence Evaluation and Its Usage for Roll-back Recovery with Checkpointing Optimization
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Scheduling Tests for 3D Stacked Chips under Power Constraints
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Test Cost Modeling for 3D Stacked Chips with Through-Silicon Vias
2011) Swedish System-on-Chip Conference, SSoCC 2011(
- Contribution to conference › Paper, not in proceeding
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Mark
SoC-Level Fault Management based on P1687 IJTAG
2011)(
- Other contribution › Miscellaneous
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Mark
Test Scheduling for 3D Stacked ICs under Power Constraints
2011) 2nd IEEE International Workshop on Reliability Aware System Design and Test (RASDAT)(
- Contribution to conference › Paper, not in proceeding