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- 2014
-
Mark
A 0.28-0.8 V 320 fW D-latch for Sub-VT Memories in 65 nm CMOS
2014) FTFC(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2013
-
Mark
Two Flavors of 4kb Standard-Cell Based Subvt Memory in 65 nm CMOS
2013) Swedish System-On-Chip Conference (SSoCC), 2013(
- Contribution to conference › Paper, not in proceeding
- 2012
-
Mark
A 500 fW/bit 14 fJ/bit-access 4kb Standard-Cell Based Sub-VT Memory in 65nm CMOS
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Integration of Full-Custom Cells in a Standard-Cell Based Flow
2012) CDNLive! EMEA, 2012(
- Contribution to conference › Paper, not in proceeding
- 2011
-
Mark
Synthesis Strategies for Sub-VT Systems
2011) 20th European Conference on Circuit Theory and Design. ECCTD 2011(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Impact of switching activity on the energy minimum voltage for 65 nm Sub-VT CMOS
2011) 29th Norchip conference, 2011(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding