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- 2014
-
Mark
A Filtering Delta Sigma ADC for LTE and Beyond
(
- Contribution to journal › Article
- 2013
-
Mark
Theory and Design of a CT Delta Sigma Modulator with Low Sensitivity to Loop-Delay Variations
(
- Contribution to journal › Article
-
Mark
A 9MHz Filtering ADC with Additional 2nd-Order Delta-Sigma Modulator Noise Suppression
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2012
-
Mark
A Continuous Time Delta-Sigma Modulator with Reduced Clock Jitter Sensitivity through DSCR Feedback
2012) In Analog Integrated Circuits and Signal Processing(
- Contribution to journal › Article
-
Mark
Harmonic Rejection Mixer at ADC Input for Complex IF Dual Carrier Receiver Architecture
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 7.5 mW 9 MHz CT Delta-Sigma Modulator in 65 nm CMOS with 69 dB SNDR and Reduced Sensitivity to Loop Delay Variations
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2011
-
Mark
A 9-band WCDMA/EDGE transceiver supporting HSPA evolution
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A continuous time delta sigma modulator with reduced clock jitter through DSCR feedback
2011) 29th Norchip conference, 2011(
- Contribution to conference › Paper, not in proceeding
- 2010
-
Mark
Impact of MOS threshold-voltage mismatch in current-steering DACs for CT delta-sigma modulators
(
- Contribution to conference › Paper, not in proceeding