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- 2020
-
Mark
Analysis and Design of a 17-GHz All-npn Push-Pull Class-C VCO
(
- Contribution to journal › Article
- 2018
-
Mark
An Accurate Analysis of Phase Noise in CMOS Ring Oscillators
(
- Contribution to journal › Article
- 2017
-
Mark
A 2.8-3.8-GHz Low-Spur DTC-Based DPLL With a Class-D DCO in 65-nm CMOS
(
- Contribution to journal › Article
-
Mark
A general theory of phase noise in transconductor-based harmonic oscillators
(
- Contribution to journal › Article
- 2015
-
Mark
Digital background calibration in continuous-time delta-sigma analog to digital converters
2015) Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 2.8-to-5.8 GHz harmonic VCO in a 28 nm UTBB FD-SOI CMOS process
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 65nm CMOS fraction-N digital PLL with shaped in-band phase noise
2015) Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 0.6-3.0 GHz 65 nm CMOS Radio Receiver with DS-based A/D-Converting Channel-Select Filters
2015) IEEE European Solid State Circuits Conference, ESSCIRC 2015(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2014
-
Mark
A Class-D CMOS DCO with an on-chip LDO
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A Power-Scalable DCO for Multi-Standard GSM/WCDMA Frequency Synthesizers
(
- Contribution to journal › Article