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- 2013
-
Mark
A 3 mu W 500 kb/s Ultra Low Power Analog Decoder with Digital I/O in 65 nm CMOS
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Next Generation Digital Front-End for Multi-Standard Concurrent Reception
2013) NORCHIP Conference, 2013(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A Highly Parallelized MIMO Detector for Vector-Based Reconfigurable Architectures
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 3 uW 500 kb/s Ultra Low Power Analog Decoder with Digital I/O in 65 nm CMOS
2013) International Conference on Electronics and Communication Systems (ICECS)(
- Contribution to conference › Paper, not in proceeding
-
Mark
Analog and Digital Design Alternatives for a Low Complexity and Power Constraint Decoder
2013)(
- Contribution to conference › Paper, not in proceeding
-
Mark
Area and Power Reduction in DFT Based Channel Estimators for OFDM Systems
2013) NORCHIP Conference, 2013(
- Contribution to conference › Paper, not in proceeding
-
Mark
Implementation of a Highly-Parallel Soft-Output MIMO Detector with Fast Node Enumeration
2013) NORCHIP Conference, 2013(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2012
-
Mark
A 0.8mm2 9.6mW Implementation of a Multicarrier Faster-Than-Nyquist Signaling Iterative Decoder in 65nm CMOS
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
High-level energy estimation in the sub-VT domain: simulation and measurement of a cardiac event detector
(
- Contribution to journal › Article
-
Mark
Mapping Channel Estimation and MIMO Detection in LTE-Advanced on a Reconfigurable Cell Array
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding