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- 2010
-
Mark
Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Thermal Aware Test Scheduling for Stacked Multi-Chip-Modules
2010) IEEE East-West Design and Test Symposium (EWDTS10)(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Graph Theoretic Approach for Scan Cell Reordering to Minimize Peak Shift Power
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Energy-Efficient Redundant Execution for Chip Multiprocessors
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
On-line Techniques to Adjust and Optimize Checkpointing Frequency
2010) IEEE International Workshop on Realiability Aware System Design and Test (RASDAT 2010) p.29-33(
- Contribution to conference › Paper, not in proceeding
-
Mark
Scheduling Tests for Stacked 3D Chips under Power Constraints
2010) Swedish SoC Conference 2010(
- Contribution to conference › Paper, not in proceeding
-
Mark
Power Constrained Test Scheduling for 3D Stacked Chips: poster
2010) 1st IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits(
- Contribution to conference › Poster
- 2009
-
Mark
Power-Aware System-Level DfT and Test Planning
2009)(
- Chapter in Book/Report/Conference proceeding › Book chapter
-
Mark
Generation of Minimal Leakage Input Vectors with Constrained NBTI Degradation
(
- Contribution to conference › Paper, not in proceeding
-
Mark
Power Efficient Redundant Execution for Chip Multiprocessors
(
- Contribution to conference › Paper, not in proceeding