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- 2011
-
Mark
Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2010
-
Mark
Ultra low energy vs throughput design exploration of 65 nm sub-VT CMOS digital filters
2010) NORCHIP Conference, 2010(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Energy efficiency in Sub-VT of various 16-bit adder structures in 65 nm CMOS
2010) Swedish System-on-Chip Conference 2010 (SSoCC'10)(
- Contribution to conference › Paper, not in proceeding
- 2009
-
Mark
Parabolic synthesis methodology implemented on the sine function
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Hardware architecture of an SVD based MIMO OFDM channel estimator
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2008
-
Mark
An Embedded Real-Time Surveillance System: Implementation and Evaluation
(
- Contribution to journal › Article
-
Mark
Arithmetic reduction of adder leakage in nanoscale CMOS
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A methodology for arithmetic reduction of the static power consumption verified on filter architectures
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
On MIMO K-best sphere detector architecture complexity reductions
2008) The 2nd International Conference on Signal Processing and Communication Systems (ICSPCS 2008) p.505-513(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A methodology for parabolic synthesis of unary functions for hardware implementation
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding