Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain
Sherazi, Syed Muhammad Yasser LU ; Nilsson, Peter LU ; Akgun, OmerCan LU ; Sjöland, Henrik LU
and Rodrigues, Joachim
LU
(2011)
IEEE International Symposium on Circuits and Systems (ISCAS 2011), 2011
p.837-840
- Abstract
- This paper presents an analysis on energy dissipation
of digital half-band filters operating in the sub-threshold
(sub-VT) region with throughput and supply voltage constraints.
A 12-bit filter is implemented along with various unfolded
structures, used to form a decimation filter chain. The designs
are synthesized in a 65 nm low-leakage CMOS technology with
various threshold voltages. A sub-VT energy model is applied to
characterize the designs in the sub-VT domain. The results show
that the low-leakage standard-threshold technology is suitable
for the required throughput range between 250Ksamples/s and
2Msamples/s, at a supply voltage of 260mV. The... (More) - This paper presents an analysis on energy dissipation
of digital half-band filters operating in the sub-threshold
(sub-VT) region with throughput and supply voltage constraints.
A 12-bit filter is implemented along with various unfolded
structures, used to form a decimation filter chain. The designs
are synthesized in a 65 nm low-leakage CMOS technology with
various threshold voltages. A sub-VT energy model is applied to
characterize the designs in the sub-VT domain. The results show
that the low-leakage standard-threshold technology is suitable
for the required throughput range between 250Ksamples/s and
2Msamples/s, at a supply voltage of 260mV. The total energy
dissipation of the filter is 205 fJ per sample. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/1759499
- author
- Sherazi, Syed Muhammad Yasser
LU
; Nilsson, Peter
LU
; Akgun, OmerCan
LU
; Sjöland, Henrik
LU
and Rodrigues, Joachim
LU
- organization
- publishing date
- 2011
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- keywords
- CMOS, sub-threshold, 65 nm, Sub-VT, Chain, low power, Ultra Low energy, Decimation Filter, Digital
- host publication
- 2011 IEEE International Symposium on Circuits and Systems (ISCAS)
- pages
- 837 - 840
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- IEEE International Symposium on Circuits and Systems (ISCAS 2011), 2011
- conference location
- Rio de Janeiro, Brazil
- conference dates
- 2011-05-15 - 2011-05-18
- external identifiers
-
- wos:000297265301019
- scopus:79960862408
- ISSN
- 0271-4310
- 2158-1525
- DOI
- 10.1109/ISCAS.2011.5937696
- language
- English
- LU publication?
- yes
- id
- 78afead6-0af3-4977-bf07-1e2fcdff8fbe (old id 1759499)
- date added to LUP
- 2016-04-01 09:57:23
- date last changed
- 2024-04-17 02:49:28
@inproceedings{78afead6-0af3-4977-bf07-1e2fcdff8fbe,
abstract = {{This paper presents an analysis on energy dissipation<br/><br>
of digital half-band filters operating in the sub-threshold<br/><br>
(sub-VT) region with throughput and supply voltage constraints.<br/><br>
A 12-bit filter is implemented along with various unfolded<br/><br>
structures, used to form a decimation filter chain. The designs<br/><br>
are synthesized in a 65 nm low-leakage CMOS technology with<br/><br>
various threshold voltages. A sub-VT energy model is applied to<br/><br>
characterize the designs in the sub-VT domain. The results show<br/><br>
that the low-leakage standard-threshold technology is suitable<br/><br>
for the required throughput range between 250Ksamples/s and<br/><br>
2Msamples/s, at a supply voltage of 260mV. The total energy<br/><br>
dissipation of the filter is 205 fJ per sample.}},
author = {{Sherazi, Syed Muhammad Yasser and Nilsson, Peter and Akgun, OmerCan and Sjöland, Henrik and Rodrigues, Joachim}},
booktitle = {{2011 IEEE International Symposium on Circuits and Systems (ISCAS)}},
issn = {{0271-4310}},
keywords = {{CMOS; sub-threshold; 65 nm; Sub-VT; Chain; low power; Ultra Low energy; Decimation Filter; Digital}},
language = {{eng}},
pages = {{837--840}},
publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
title = {{Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain}},
url = {{http://dx.doi.org/10.1109/ISCAS.2011.5937696}},
doi = {{10.1109/ISCAS.2011.5937696}},
year = {{2011}},
}