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- 2008
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Mark
Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Eclipse Plugin for Bluespec System Verilog
2008)(
- Book/Report › Report
-
Mark
Non-uniform fractional tessellation
2008) p.41-45(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
High-Level GPU Programming: Domain-Specific Optimization and Inference
2008)(
- Thesis › Doctoral thesis (compilation)
-
Mark
Optimization of Routing and Reconfiguration Overhead in Programmable Processor Array Architectures
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
VHDL vs. Bluespec System Verilog: A case study on a Java embedded architecture
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Exact graph coloring using inclusion–exclusion
2008) p.289-290(
- Chapter in Book/Report/Conference proceeding › Book chapter
-
Mark
Load-balancing methods for parallel constraint solving
2008) International Conference on Principles and Practice of Constraint Programming: Doctoral Program(
- Contribution to conference › Paper, not in proceeding
-
Mark
Automatic Selection of Application-Specific Reconfigurable Processor Extensions
2008) Intl. Conference on Design, Automation and Test in Europe (DATE)(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Floating-point buffer compression in a unified codec architecture
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding