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2014
Mark Test Planning and Test Access Mechanism Design for Stacked Chips using ILP
Sengupta, Breeta ^LU and Larsson, Erik ^LU (2014) IEEE VLSI Test Symposium (VTS) p.1-6
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
Mark Test Planning and Test Access Mechanism Design for 3D SICs
Sengupta, Breeta ^LU and Larsson, Erik ^LU (2014) Swedish System on Chip Conference (SSoCC), 2014
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
2013
Mark Test Planning for 3D SICs using ILP
Sengupta, Breeta ^LU and Larsson, Erik ^LU (2013) Swedish System-On-Chip Conference (SSoCC), 2013
- Contribution to conference › Paper, not in proceeding
2012
Mark Test Planning for Core-based 3D Stacked ICs under Power Constraints
Sengupta, Breeta ^LU ; Ingelsson, Urban and Larsson, Erik ^LU (2012) IEEE International Workshop on Realiability Aware System Design and Test (RASDAT 2012)
- Contribution to conference › Paper, not in proceeding
2011
Mark Scheduling Tests for 3D Stacked Chips under Power Constraints
Sengupta, Breeta ^LU ; Ingelsson, Urban and Larsson, Erik ^LU (2011) 6th International Symposium on Electronic Design, Test and Applications (DELTA 2011) p.72-77
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
Mark Test Scheduling for 3D Stacked ICs under Power Constraints
Sengupta, Breeta ^LU ; Ingelsson, Urban and Larsson, Erik ^LU (2011) 2nd IEEE International Workshop on Reliability Aware System Design and Test (RASDAT)
- Contribution to conference › Paper, not in proceeding
Mark Test Cost Modeling for 3D Stacked Chips with Through-Silicon Vias
Sengupta, Breeta ^LU ; Ingelsson, Urban and Larsson, Erik ^LU (2011) Swedish System-on-Chip Conference, SSoCC 2011
- Contribution to conference › Paper, not in proceeding
2010
Mark Scheduling Tests for Stacked 3D Chips under Power Constraints
Sengupta, Breeta ^LU ; Ingelsson, Urban and Larsson, Erik ^LU (2010) Swedish SoC Conference 2010
- Contribution to conference › Paper, not in proceeding