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        - 2022
- 
                        Mark
        A 12-GHz Reconfigurable Multicore CMOS DCO, With a Time-Variant Analysis of the Impact of Reconfiguration Switches on Phase Noise
    
    - Contribution to journal › Article
 
- 2017
- 
                        Mark
        A 2.8-3.8-GHz Low-Spur DTC-Based DPLL With a Class-D DCO in 65-nm CMOS
    
    - Contribution to journal › Article
 
- 2011
- 
                        Mark
        A 5GHz 90-nm CMOS all digital phase-locked loop
    
    - Contribution to journal › Article
 
- 2009
- 
                        Mark
        A 5GHz 90-nm CMOS all digital phase-locked loop
    
    - Contribution to conference › Paper, not in proceeding
 
