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- 2011
-
Mark
Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2003
-
Mark
Custom Datapaths for DSP ASICs Methodology and Implementation
2003)(
- Thesis › Doctoral thesis (compilation)
- 1999
-
Mark
Power Reduction in Custom CMOS Digital Filter Structures
(
- Contribution to journal › Article
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