Breeta Sengupta (Former)
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- 2020
-
Mark
Test Cost Reduction of 3D Stacked ICs : Test Planning and Test Flow Selection
2020)(
- Thesis › Doctoral thesis (monograph)
- 2019
-
Mark
Test Flow Selection for Stacked Integrated Circuits
(
- Contribution to journal › Article
- 2017
-
Mark
Test Planning for Core-based Integrated Circuits under Power Constraints
(
- Contribution to journal › Article
- 2014
-
Mark
Test Planning and Test Access Mechanism Design for Stacked Chips using ILP
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Test Planning and Test Access Mechanism Design for 3D SICs
2014) Swedish System on Chip Conference (SSoCC), 2014(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding