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- 2019
-
Mark
Test Flow Selection for Stacked Integrated Circuits
(
- Contribution to journal › Article
- 2017
-
Mark
Test Planning for Core-based Integrated Circuits under Power Constraints
(
- Contribution to journal › Article
- 2014
-
Mark
Test Planning and Test Access Mechanism Design for Stacked Chips using ILP
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Test Planning and Test Access Mechanism Design for 3D SICs
2014) Swedish System on Chip Conference (SSoCC), 2014(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2013
-
Mark
Test Planning for 3D SICs using ILP
2013) Swedish System-On-Chip Conference (SSoCC), 2013(
- Contribution to conference › Paper, not in proceeding
- 2012
-
Mark
Scheduling Tests for 3D Stacked Chips under Power Constraints
(
- Contribution to journal › Article
-
Mark
Test Planning for Core-based 3D Stacked ICs under Power Constraints
2012) IEEE International Workshop on Realiability Aware System Design and Test (RASDAT 2012)(
- Contribution to conference › Paper, not in proceeding
-
Mark
Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2011
-
Mark
Test Scheduling for 3D Stacked ICs under Power Constraints
2011) 2nd IEEE International Workshop on Reliability Aware System Design and Test (RASDAT)(
- Contribution to conference › Paper, not in proceeding
-
Mark
Test Planning for 3D Stacked ICs with Through-Silicon Vias
2011) Second IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits(
- Contribution to conference › Paper, not in proceeding