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- 2020
-
Mark
High-Level Synthesis for Efficient Design and Verification
- Master (Two yrs)
- 2019
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Mark
Case study on Universal Verification Methodology(UVM) SystemC testbench for RTL verification
- Master (Two yrs)
-
Mark
Performance Evaluation of MathWorks HDL Coder as a Vendor Independent DFE Generation
- Master (Two yrs)
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Mark
Investigate Redundancy In Sounding Reference Signal Based Channel Estimates
- Master (Two yrs)
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Mark
Arbitrary Decimation for High Sample Rates, Algorithm Design and FPGA implementation
- Master (Two yrs)
-
Mark
Implementation of an 8-bit Dynamic Fixed-Point Convolutional Neural Network for Human Sign Language Recognition on a Xilinx FPGA Board
- Master (Two yrs)
-
Mark
Reduction of Crosstalk Distortion in 5G
- Master (Two yrs)
- 2018
-
Mark
Efficient DPD Coefficient Extraction For Compensating Antenna Crosstalk And Mismatch Effects In Advanced Antenna System
- Master (Two yrs)
-
Mark
Hardware-software model co-simulation for GPU IP development
- Master (Two yrs)
-
Mark
RF system for mmWave massive MIMO
- Master (Two yrs)