A sequential logic device realized by integration of in-plane gate transistors in InGaAs/InP
(2008) In Applied Physics Letters 92(1).- Abstract
- An integrated nanoelectronic circuit is fabricated from a high-mobility In0.75Ga0.25As/InP heterostructure. The manufactured device comprises two double in-plane gate transistors with a current channel of 1.1 mu m in length and 100 nm in width. The two transistors are coupled to each other in a configuration that the source of one transistor is directly connected with one in-plane gate of the other transistor. Electrical measurements reveal that this device functions as an SR (set-reset) latch (a sequential logic device) with a gain of similar to 4 in the logic swing at room temperature. The demonstrated device provides a simple circuit design for SR latches.
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/1199990
- author
- Sun, Jie LU ; Wallin, Daniel LU ; He, Yuhui ; Maximov, Ivan LU and Xu, Hongqi LU
- organization
- publishing date
- 2008
- type
- Contribution to journal
- publication status
- published
- subject
- in
- Applied Physics Letters
- volume
- 92
- issue
- 1
- article number
- 012116
- publisher
- American Institute of Physics (AIP)
- external identifiers
-
- wos:000252284200084
- scopus:38049072561
- ISSN
- 0003-6951
- DOI
- 10.1063/1.2825575
- language
- English
- LU publication?
- yes
- id
- e7e47b89-a2e6-457c-8cc5-0f100845286a (old id 1199990)
- date added to LUP
- 2016-04-01 11:56:22
- date last changed
- 2022-01-26 20:27:17
@article{e7e47b89-a2e6-457c-8cc5-0f100845286a, abstract = {{An integrated nanoelectronic circuit is fabricated from a high-mobility In0.75Ga0.25As/InP heterostructure. The manufactured device comprises two double in-plane gate transistors with a current channel of 1.1 mu m in length and 100 nm in width. The two transistors are coupled to each other in a configuration that the source of one transistor is directly connected with one in-plane gate of the other transistor. Electrical measurements reveal that this device functions as an SR (set-reset) latch (a sequential logic device) with a gain of similar to 4 in the logic swing at room temperature. The demonstrated device provides a simple circuit design for SR latches.}}, author = {{Sun, Jie and Wallin, Daniel and He, Yuhui and Maximov, Ivan and Xu, Hongqi}}, issn = {{0003-6951}}, language = {{eng}}, number = {{1}}, publisher = {{American Institute of Physics (AIP)}}, series = {{Applied Physics Letters}}, title = {{A sequential logic device realized by integration of in-plane gate transistors in InGaAs/InP}}, url = {{http://dx.doi.org/10.1063/1.2825575}}, doi = {{10.1063/1.2825575}}, volume = {{92}}, year = {{2008}}, }